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Berkeley COMPSCI 152 - Multicycle Controller Design

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10/05/01 ©UCB Fall 2001CS152 /Kubiatowicz Lec11.1CS 152 Computer Architecture and EngineeringLecture 11Multicycle Controller Design October 5, 2001John Kubiatowicz (http.cs.berkeley.edu/~kubitron)lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/10/05/01 ©UCB Fall 2001CS152 /Kubiatowicz Lec11.2Overview of Control° Control may be designed using one of several initial representations. The choice of sequence control, and how logic is represented, can then be determined independently; the control can then be implemented with one of several methods using a structured logic technique.Initial Representation Finite State Diagram MicroprogramSequencing Control Explicit Next State Microprogram counterFunction + Dispatch ROMs Logic Representation Logic Equations Truth TablesImplementation PLA ROM Technique“hardwired control” “microprogrammed control”10/05/01 ©UCB Fall 2001CS152 /Kubiatowicz Lec11.3Recap: “Macroinstruction” InterpretationMainMemoryexecutionunitcontrolmemoryCPUADDSUBANDDATA...User program plus Datathis can change!AND microsequencee.g., FetchCalc Operand AddrFetch Operand(s)CalculateSave Answer(s)one of these ismapped into oneof these10/05/01 ©UCB Fall 2001CS152 /Kubiatowicz Lec11.4Recap: Micro-controller Design° The state digrams that arise define the controller for an instruction set processor are highly structured° Use this structure to construct a simple “microsequencer” • Each state in previous diagram becomes a “microinstruction”• Microinstructions often taken sequentially° Control reduces to programming this devicesequencercontroldatapath controlmicro-PCsequencermicroinstruction (µ)10/05/01 ©UCB Fall 2001CS152 /Kubiatowicz Lec11.5The Big Picture: Where are We Now? ° The Five Classic Components of a Computer° Today’s Topics:• Microprogramed control• Administrivia; Courses• Microprogram it yourself• Exceptions• Intro to Pipelining (if time permits)ControlDatapathMemoryProcessorInputOutput10/05/01 ©UCB Fall 2001CS152 /Kubiatowicz Lec11.6Recap: Horizontal vs. Vertical MicroprogrammingNOTE: previous organization is not TRUE horizontal microprogramming;register decoders give flavor of encoded microoperationsMost microprogramming-based controllers vary between:horizontal organization (1 control bit per control point)vertical organization (fields encoded in the control memory and must be decoded to control something)Horizontal+ more control over the potentialparallelism of operations in thedatapath- uses up lots of control storeVertical+ easier to program, not verydifferent from programminga RISC machine in assemblylanguage- extra level of decoding mayslow the machine down10/05/01 ©UCB Fall 2001CS152 /Kubiatowicz Lec11.7Recap: Designing a Microinstruction Set1) Start with list of control signals2) Group signals together that make sense (vs. random): called “fields”3) Places fields in some logical order (e.g., ALU operation & ALU operands first andmicroinstruction sequencing last)4) Create a symbolic legend for the microinstruction format, showing name of field values and how they set the control signals• Use computers to design computers5) To minimize the width, encode operations that will never be used at the same time10/05/01 ©UCB Fall 2001CS152 /Kubiatowicz Lec11.8Alternative datapath (book): Multiple Cycle Datapath° Miminizes Hardware: 1 memory, 1 adderIdealMemoryWrAdrDinRAdr323232DoutMemWr32ALU3232ALUOpALUControl32IRWrInstruction Reg32Reg FileRaRwbusWRb5532busA32busBRegWrRsRtMux01RtRdPCWrALUSelAMux01RegDstMux0132PCMemtoRegExtendExtOpMux01320123416Imm32<< 2ALUSelBMux1032ZeroZeroPCWrCondPCSrc32IorDMem Data RegALU OutBA10/05/01 ©UCB Fall 2001CS152 /Kubiatowicz Lec11.91&2) Start with list of control signals, grouped into fieldsSignal name Effect when deasserted Effect when assertedALUSelA 1st ALU operand = PC 1st ALU operand = Reg[rs]RegWrite None Reg. is writtenMemtoReg Reg. write data input = ALU Reg. write data input = memoryRegDst Reg. dest. no. = rt Reg. dest. no. = rdMemRead None Memory at address is read, MDR <= Mem[addr]MemWrite None Memory at address is writtenIorD Memory address = PC Memory address = SIRWrite None IR <= MemoryPCWrite None PC <= PCSourcePCWriteCond None IF ALUzero then PC <= PCSourcePCSource PCSource = ALU PCSource = ALUoutExtOp Zero Extended Sign Extended Single Bit ControlSignal name Value EffectALUOp 00 ALU adds 01 ALU subtracts 10 ALU does function code11 ALU does logical ORALUSelB 00 2nd ALU input = 401 2nd ALU input = Reg[rt] 10 2nd ALU input = extended,shift left 2 11 2nd ALU input = extendedMultiple Bit Control10/05/01 ©UCB Fall 2001CS152 /Kubiatowicz Lec11.104) Legend of Fields and Symbolic NamesField Name Values for Field Function of Field with Specific ValueALU Add ALU addsSubt. ALU subtractsFunc code ALU does function codeOr ALU does logical ORSRC1 PC 1st ALU input = PCrs 1st ALU input = Reg[rs]SRC2 4 2nd ALU input = 4Extend 2nd ALU input = sign ext. IR[15-0]Extend0 2nd ALU input = zero ext. IR[15-0]Extshft 2nd ALU input = sign ex., sl IR[15-0]rt 2nd ALU input = Reg[rt]destination rd ALU Reg[rd] = ALUout rt ALU Reg[rt] = ALUoutrt Mem Reg[rt] = Mem Memory Read PC Read memory using PCRead ALU Read memory using ALUout for addrWrite ALU Write memory using ALUout for addrMemory register IR IR = MemPC write ALU PC = ALUALUoutCond IF ALU Zero then PC = ALUoutSequencing Seq Go to sequential µinstructionFetch Go to the first microinstructionDispatch Dispatch using ROM.10/05/01 ©UCB Fall 2001CS152 /Kubiatowicz Lec11.11Quick check: what do these fieldnames mean?Code Name RegWrite MemToReg RegDest00 --- 0 X X01 rd ALU 1 0 110 rt ALU 1 0 011 rt MEM 1 1 0Code Name ALUSelB ExtOp000 --- X X001 4 00 X010 rt 01 X011 ExtShft 10 1100 Extend 11 1111 Extend0 11 0Destination:SRC2:10/05/01 ©UCB Fall 2001CS152 /Kubiatowicz Lec11.123) Microinstruction Format: unencoded vs. encoded fieldsField Name Width Control Signals Setwide narrowALU Control 4 2 ALUOpSRC1 2 1 ALUSelASRC2 5 3 ALUSelB, ExtOpALU Destination 3 2 RegWrite, MemtoReg, RegDstMemory 3 2 MemRead, MemWrite, IorDMemory Register 1 1 IRWritePCWrite Control 3 2 PCWrite, PCWriteCond, PCSourceSequencing 3 2 AddrCtlTotal width 24 15 bits10/05/01 ©UCB Fall 2001CS152 /Kubiatowicz Lec11.13Alternative datapath (book): Multiple Cycle Datapath° Miminizes Hardware: 1 memory, 1 adderIdealMemoryWrAdrDinRAdr323232DoutMemWr32ALU3232ALUOpALUControl32IRWrInstruction Reg32Reg


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Berkeley COMPSCI 152 - Multicycle Controller Design

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