Overview of Control CS 152 Computer Architecture and Engineering Lecture 11 Multicycle Controller Design Control may be designed using one of several initial representations The choice of sequence control and how logic is represented can then be determined independently the control can then be implemented with one of several methods using a structured logic technique Initial Representation Sequencing Control October 5 2001 Finite State Diagram Microprogram Explicit Next State Microprogram counter Function Dispatch ROMs John Kubiatowicz http cs berkeley edu kubitron Logic Representation Logic Equations Implementation Technique hardwired control Truth Tables lecture slides http www inst eecs berkeley edu cs152 10 05 01 CS152 Kubiatowicz Lec11 1 UCB Fall 2001 Recap Macroinstruction Interpretation Main Memory ADD SUB AND DATA execution unit CPU 10 05 01 ROM microprogrammed control UCB Fall 2001 CS152 Kubiatowicz Lec11 2 Recap Micro controller Design User program plus Data this can change one of these is mapped into one of these The state digrams that arise define the controller for an instruction set processor are highly structured Use this structure to construct a simple microsequencer Each state in previous diagram becomes a microinstruction Microinstructions often taken sequentially Control reduces to programming this device sequencer control AND microsequence control memory PLA e g Fetch Calc Operand Addr Fetch Operand s Calculate Save Answer s datapath control microinstruction micro PC sequencer 10 05 01 UCB Fall 2001 CS152 Kubiatowicz Lec11 3 10 05 01 UCB Fall 2001 CS152 Kubiatowicz Lec11 4 The Big Picture Where are We Now Recap Horizontal vs Vertical Microprogramming NOTE previous organization is not TRUE horizontal microprogramming register decoders give flavor of encoded microoperations The Five Classic Components of a Computer Most microprogramming based controllers vary between Processor Input horizontal organization 1 control bit per control point Control vertical organization fields encoded in the control memory and must be decoded to control something Memory Datapath Output Today s Topics 10 05 01 Microprogramed control Administrivia Courses Microprogram it yourself Exceptions Intro to Pipelining if time permits UCB Fall 2001 Horizontal Vertical more control over the potential parallelism of operations in the datapath easier to program not very different from programming a RISC machine in assembly language CS152 Kubiatowicz Lec11 5 uses up lots of control store 10 05 01 Recap Designing a Microinstruction Set extra level of decoding may slow the machine down CS152 Kubiatowicz Lec11 6 UCB Fall 2001 Alternative datapath book Multiple Cycle Datapath Miminizes Hardware 1 memory 1 adder 1 Start with list of control signals PCWr PC Rs ALUSelA RegWr 0 32 RAdr WrAdr 32 Din Dout 32 32 Use computers to design computers 5 32 Rt 5 Rt 0 Rd Mux Ideal Memory 1 Mem Data Reg 32 0 Ra busA A Rb Reg File Rw busW busB 1 1 Mux 0 2 0 Extend ExtOp 32 32 0 1 32 32 2 3 ALU Control 10 05 01 UCB Fall 2001 CS152 Kubiatowicz Lec11 7 10 05 01 UCB Fall 2001 32 MemtoReg Zero 32 5 To minimize the width encode operations that will never be used at the same time Imm 16 32 1 4 B 1 ALU Out RegDst ALU IRWr Mux 32 Mux 4 Create a symbolic legend for the microinstruction format showing name of field values and how they set the control signals MemWr 32 Mux IorD 3 Places fields in some logical order e g ALU operation ALU operands first and microinstruction sequencing last PCSrc PCWrCond Zero Instruction Reg 2 Group signals together that make sense vs random called fields ALUOp ALUSelB CS152 Kubiatowicz Lec11 8 Multiple Bit Control Single Bit Control 1 2 Start with list of control signals grouped into fields Signal name ALUSelA RegWrite MemtoReg RegDst MemRead Effect when deasserted Effect when asserted 1st ALU operand PC 1st ALU operand Reg rs None Reg is written Reg write data input ALU Reg write data input memory Reg dest no rt Reg dest no rd None Memory at address is read MDR Mem addr MemWrite None Memory at address is written IorD Memory address PC Memory address S IRWrite None IR Memory PCWrite None PC PCSource PCWriteCond None IF ALUzero then PC PCSource PCSource PCSource ALU PCSource ALUout ExtOp Zero Extended Sign Extended Signal name Value ALUOp 00 01 10 11 ALUSelB 00 01 10 11 10 05 01 Effect ALU adds ALU subtracts ALU does function code ALU does logical OR 2nd ALU input 4 2nd ALU input Reg rt 2nd ALU input extended shift left 2 2nd ALU input extended UCB Fall 2001 CS152 Kubiatowicz Lec11 9 Quick check what do these fieldnames mean 4 Legend of Fields and Symbolic Names Field Name ALU Values for Field Add Subt Func code Or SRC1 PC rs SRC2 4 Extend Extend0 Extshft rt destination rd ALU rt ALU rt Mem Memory Read PC Read ALU Write ALU Memory register IR PC write ALU ALUoutCond Sequencing Seq Fetch Dispatch 10 05 01 Function of Field with Specific Value ALU adds ALU subtracts ALU does function code ALU does logical OR 1st ALU input PC 1st ALU input Reg rs 2nd ALU input 4 2nd ALU input sign ext IR 15 0 2nd ALU input zero ext IR 15 0 2nd ALU input sign ex sl IR 15 0 2nd ALU input Reg rt Reg rd ALUout Reg rt ALUout Reg rt Mem Read memory using PC Read memory using ALUout for addr Write memory using ALUout for addr IR Mem PC ALU IF ALU Zero then PC ALUout Go to sequential instruction Go to the first microinstruction Dispatch using ROM UCB Fall 2001 CS152 Kubiatowicz Lec11 10 3 Microinstruction Format unencoded vs encoded fields Destination Code 00 01 10 11 Name rd ALU rt ALU rt MEM RegWrite 0 1 1 1 MemToReg X 0 0 1 RegDest X 1 0 0 SRC2 Code 000 001 010 011 100 111 10 05 01 Name 4 rt ExtShft Extend Extend0 ALUSelB X 00 01 10 11 11 ExtOp X X X 1 1 0 UCB Fall 2001 CS152 Kubiatowicz Lec11 11 Field Name Width Control Signals Set wide narrow ALU Control 4 2 ALUOp SRC1 2 1 ALUSelA SRC2 5 3 ALUSelB ExtOp ALU Destination 3 2 RegWrite MemtoReg RegDst Memory 3 2 MemRead MemWrite IorD Memory Register 1 1 IRWrite PCWrite Control 3 2 PCWrite PCWriteCond PCSource Sequencing 3 2 AddrCtl Total width 24 15 10 05 01 bits UCB Fall 2001 CS152 Kubiatowicz Lec11 12 Alternative datapath book Multiple Cycle Datapath Finite State Machine FSM Spec Miminizes Hardware 1 memory 1 adder IR MEM PC instruction fetch PC PC 4 Rs ALUSelA RegWr PC 0 RAdr 32 WrAdr 32 Din Dout 32 32 5 Rt 0 Rd Mux Ideal Memory 1 5 32 Rt Mem Data Reg Mux 32 0 Mux 32 Ra busA A Rb Reg File Rw busW busB 1 1 Mux 0 32 32 Zero 32 2 32 R type LW ORi ALUout A fun B ALUout A or
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