CS152 Computer Architecture and Engineering Lecture 4 Cost and DesignReview: Performance and Technology TrendsReview: Technology, Logic Design and DelayOverview: Cost and DesignIntegrated Circuit CostsDie YieldReal World ExamplesOther CostsSystem Cost: 1995-96 WorkstationSlide 10Cost SummaryAdministrative MattersThe Design ProcessDesign Process (cont.)Design RefinementDesign as SearchProblem: Design a “fast” ALU for the MIPS ISAMIPS ALU requirementsMIPS arithmetic instruction formatDesign Trick: divide & conquerRefined RequirementsBehavioral Representation: VHDLDesign DecisionsRefined Diagram: bit-slice ALU7-to-2 Combinational LogicSeven plus a MUX ?Additional operationsRevised DiagramOverflowOverflow DetectionOverflow Detection LogicMore Revised DiagramBut What about Performance?Carry Look Ahead (Design trick: peek)Plumbing as Carry Lookahead AnalogyCascaded Carry Look-ahead (16-bit): Abstraction2nd level Carry, Propagate as PlumbingDesign Trick: Guess (or “Precompute”)Carry Skip Adder: reduce worst case delayAdditional MIPS ALU requirementsElements of the Design ProcessSummary of the Design ProcessWhy should you keep an design notebook?Why do we keep it on-line?How should you do it?On-line Notebook Example1st page of On-line notebook (Index + Wed. 9/6/95)2nd page of On-line notebook (Thursday 9/7/95)3rd page of On-line notebook (Monday 9/11/95)4th page of On-line notebook (9/11/95 contd)5th page of On-line notebook (9/11/95 contd)Added benefit: cool post-design statisticsLecture Summary2/3/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec4.1Feb 3, 1999John Kubiatowicz (http.cs.berkeley.edu/~kubitron)lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/CS152Computer Architecture and EngineeringLecture 4Cost and Design2/3/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec4.2YearPerformance0.111010010001965 1970 1975 1980 1985 1990 1995 2000MicroprocessorsMinicomputersMainframesSupercomputersReview: Performance and Technology Trends°Technology Power: 1.2 x 1.2 x 1.2 = 1.7 x / year•Feature Size: shrinks 10% / yr. => Switching speed improves 1.2 / yr.•Density: improves 1.2x / yr.•Die Area: 1.2x / yr.°RISC lesson is to keep the ISA as simple as possible:•Shorter design cycle => fully exploit the advancing technology (~3yr)•Advanced branch prediction and pipeline techniques•Bigger and more sophisticated on-chip caches2/3/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec4.3Review: Technology, Logic Design and Delay°CMOS Technology Trends•Complementary: PMOS and NMOS transistors•CMOS inverter and CMOS logic gates°Delay Modeling and Gate Characterization•Delay = Internal Delay + (Load Dependent Delay x Output Load)°Clocking Methodology and Timing Considerations•Simplest clocking methodology-All storage elements use the SAME clock edge•Cycle Time = CLK-to-Q + Longest Delay Path + Setup + Clock Skew•(CLK-to-Q + Shortest Delay Path - Clock Skew) > Hold Time2/3/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec4.4Overview: Cost and Design°Review from Last Lecture (2 minutes)°Cost and Price (18)°Administrative Matters (3 minutes)°Design process (27 minutes)°Break (5 minutes)°More Design process (15 minutes)°Online notebook (10 minutes)2/3/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec4.5Defects_per_unit_area * Die_Area }Integrated Circuit CostsDie Cost is goes roughly with the cube of the area.{ 1+Die cost = Wafer cost Dies per Wafer * Die yieldDies per wafer = * ( Wafer_diam / 2)2 – * Wafer_diam – Test dies Wafer Area Die Area 2 * Die Area Die Area Die Yield = Wafer yield2/3/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec4.6Die YieldRaw Dice Per Waferwafer diameter die area (mm2)100 144 196 256 324 4006”/15cm 139 90 62 44 32 23 8”/20cm 265 177 124 90 68 52 10”/25cm 431 290 206 153 116 90 die yield 23% 19% 16% 12% 11% 10%typical CMOS process: =2, wafer yield=90%, defect density=2/cm2, 4 test sites/waferGood Dice Per Wafer (Before Testing!)6”/15cm 31 16 9 5 3 2 8”/20cm 59 32 19 11 7 510”/25cm 96 53 32 20 13 9typical cost of an 8”, 4 metal layers, 0.5um CMOS wafer: ~$20002/3/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec4.7Real World ExamplesChip MetalLineWaferDefect AreaDies/YieldDie Costlayers widthcost/cm2mm2wafer386DX 2 0.90$900 1.0 43 360 71% $4 486DX2 30.80$1200 1.0 81 181 54%$12 PowerPC 601 40.80$1700 1.3 121 115 28%$53 HP PA 7100 30.80$1300 1.0 196 66 27% $73 DEC Alpha 30.70$1500 1.2 234 53 19%$149 SuperSPARC 30.70$1700 1.6 256 48 13%$272 Pentium 30.80$1500 1.5 296 40 9%$417 From "Estimating IC Manufacturing Costs,” by Linley Gwennap, Microprocessor Report, August 2, 1993, p. 152/3/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec4.8IC cost = Die cost + Testing cost + Packaging cost Final test yieldPackaging Cost: depends on pins, heat dissipationOther CostsChip Die Package Test & Totalcost pins type cost Assembly386DX $4 132 QFP $1 $4 $9 486DX2 $12 168 PGA $11 $12 $35 PowerPC 601 $53 304 QFP $3 $21 $77 HP PA 7100 $73 504 PGA $35 $16 $124 DEC Alpha $149 431 PGA $30 $23 $202 SuperSPARC $272 293 PGA $20 $34 $326 Pentium $417 273 PGA $19 $37 $4732/3/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec4.9System Cost: 1995-96 Workstation System Subsystem% of total costCabinet Sheet metal, plastic1%Power supply, fans 2%Cables, nuts, bolts 1%(Subtotal) (4%)Motherboard Processor6%DRAM (64MB) 36%Video system 14%I/O system 3%Printed Circuit board 1% (Subtotal) (60%)I/O Devices Keyboard, mouse1%Monitor 22%Hard disk (1 GB) 7%Tape drive (DAT) 6% (Subtotal) (36%)2/3/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec4.10ComponentCostcomponentcostDirect Costscomponentcostdirect costsGross Margincomponentcostdirect costsgross marginAverageDiscountlist priceavg. selling priceInput: chips, displays, ...Making it: labor, scrap, returns, ...Overhead: R&D, rent, marketing, profits, ...Commision: channel profit, volume discounts,+33%+25–100%+50–80%(25–31%)(33–45%)(8–10%)(33–14%)(WS–PC)Q: What % of company incomeon Research and Development (R&D)?Cost vs. Price2/3/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec4.11Cost Summary°Integrated circuits driving computer industry°Die costs goes up with the cube of die area°Economics ($$$) is the ultimate driver for performance!2/3/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec4.12Administrative Matters°Review complete: did ok on prob 1 & 4.
View Full Document