CS 152 Computer Architecture and Engineering Lecture 12 Complex Pipelines Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http www eecs berkeley edu krste http inst eecs berkeley edu cs152 Last time in Lecture 11 Modern page based virtual memory systems provide Translation Protection Virtual memory to allow main memory to act as a cache of a larger disk memory equivalent Translation and protection information stored in page tables held in main memory Translation and protection information cached in translation lookaside buffer TLB to provide single cycle translation protection check in common case VM interacts with cache design Physical cache tags require address translation before tag lookup or use untranslated offset bits to index cache Virtual tags do not require translation before cache hit miss determination but need to be flushed or extended with ASID to cope with context swaps Also must deal with virtual address aliases usually by disallowing copies in cache 3 11 2008 CS152 Spring 08 2 Complex Pipelining Motivation Pipelining becomes complex when we want high performance in the presence of Long latency or partially pipelined floating point units Multiple arithmetic and memory units Memory systems with variable access time 3 11 2008 CS152 Spring 08 3 Floating Point ISA Interaction between the floating point datapath and the integer datapath is determined largely by the ISA MIPS ISA separate register files for FP and Integer instructions the only interaction is via a set of move instructions some ISA s don t even permit this separate load store for FPR s and GPR s but both use GPR s for address calculation separate conditions for branches FP branches are defined in terms of condition codes 3 11 2008 CS152 Spring 08 4 Floating Point Unit Much more hardware than an integer unit Single cycle floating point unit is a bad idea why it is common to have several floating point units it is common to have different types of FPU s Fadd Fmul Fdiv an FPU may be pipelined partially pipelined or not pipelined To operate several FPU s concurrently the register file needs to have more read and write ports 3 11 2008 CS152 Spring 08 5 Function Unit Characteristics fully pipelined partially pipelined busy 1cyc1cyc1cyc accept busy 2 cyc 2 cyc accept Function units have internal pipeline registers operands are latched when an instruction enters a function unit inputs to a function unit e g register file can change during a long latency operation 3 11 2008 CS152 Spring 08 6 Realistic Memory Systems Latency of access to the main memory is usually much greater than one cycle and often unpredictable Solving this problem is a central issue in computer architecture Common approaches to improving memory performance separate instruction and data memory ports no self modifying code caches single cycle except in case of a miss stall interleaved memory multiple memory accesses bank conflicts split phase memory operations out of order responses 3 11 2008 CS152 Spring 08 7 Complex Pipeline Structure ALU IF ID Issue GPR s FPR s Mem WB Fadd Fmul Fdiv 3 11 2008 CS152 Spring 08 8 Complex Pipeline Control Issues Structural conflicts at the execution stage if some FPU or memory unit is not pipelined and takes more than one cycle Structural conflicts at the write back stage due to variable latencies of different function units Out of order write hazards due to variable latencies of different function units How to handle exceptions 3 11 2008 CS152 Spring 08 9 Complex In Order Pipeline PC Inst Mem D Decode Delay writeback so all operations have same latency to W stage GPRs FPRs X1 X1 X2 Data Mem X3 W X2 Fadd X3 W Write ports never oversubscribed one inst in one inst out every cycle X2 How to prevent increased writeback latency from slowing down single cycle integer operations 3 11 2008 Fmul X3 Commit Point Unpipelined FDiv X2 CS152 Spring 08 divider X3 10 Complex In Order Pipeline PC Inst Mem D Decode How should we handle data hazards for very long latency operations GPRs FPRs X1 X1 X2 Data Mem X3 W X2 Fadd X3 W X2 Fmul X3 Commit Point Unpipelined FDiv X2 3 11 2008 CS152 Spring 08 divider X3 11 Superscalar In Order Pipeline PC Inst 2 D Mem Dual Decode Fetch two instructions per cycle issue both simultaneously if one is integer memory and other is floating point Inexpensive way of increasing throughput examples include Alpha 21064 1992 MIPS R5000 series 1996 Same idea can be extended to wider issue by duplicating functional units e g 4 issue UltraSPARC but register file ports and bypassing costs grow quickly 3 11 2008 GPRs FPRs X1 X1 X2 Data Mem X3 W X2 Fadd X3 W X2 Fmul X3 Commit Point Unpipelined FDiv X2 CS152 Spring 08 divider X3 12 Dependence Analysis Types of Data Hazards Consider executing a sequence of rk ri op rj type of instructions Data dependence r3 r1 op r2 Read after Write r5 r3 op r4 RAW hazard Anti dependence r3 r1 op r2 Write after Read r1 r4 op r5 WAR hazard Output dependence r3 r1 op r2 r3 r6 op r7 3 11 2008 CS152 Spring 08 Write after Write WAW hazard 14 Detecting Data Hazards Range and Domain of instruction i R i Registers or other storage modified by instruction i D i Registers or other storage read by instruction i Suppose instruction j follows instruction i in the program order Executing instruction j before the effect of instruction i has taken place can cause a R j R j RAW hazard if R i D j WAR hazard if D i WAW hazard if R i 3 11 2008 CS152 Spring 08 15 Register vs Memory Data Dependence Data hazards due to register operands can be determined at the decode stage but data hazards due to memory operands can be determined only after computing the effective address store load M r1 disp1 r2 r3 M r4 disp2 Does r1 disp1 r4 disp2 3 11 2008 CS152 Spring 08 16 Data Hazards An Example I1 DIVD f6 f6 f4 I2 LD f2 45 r3 I3 MULTD f0 f2 f4 I4 DIVD f8 f6 f2 I5 SUBD f10 f0 f6 I6 ADDD f6 f8 f2 RAW Hazards WAR Hazards WAW Hazards 3 11 2008 CS152 Spring 08 17 Instruction Scheduling I1 DIVD f6 f6 I2 LD f2 45 r3 I3 MULTD f0 f2 f4 I4 DIVD f8 f6 f2 I5 SUBD f10 f0 f6 I6 ADDD f6 f8 f4 I1 I2 I3 I4 f2 Valid orderings in order I1 I2 I3 I4 I5 I6 I2 I1 I3 I4 I5 I6 I1 I2 I3 I5 I4 I6 out of order out of order 3 11 2008 CS152 Spring 08 I5 I6 18 Out of order Completion In order Issue I1 DIVD f6 f6 I2 LD f2 45 r3 I3 MULTD f0 f2 f4 3 I4 DIVD f8 f6 f2 4 I5 SUBD f10 f0 f6 1 I6 ADDD f6 f8 f2 1 in order comp 1 2 out of order comp 1 2 3 11 2008 f4 Latency 4 1 1 2 3 4 3 …
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