Outline of Today s Lecture CS152 Computer Architecture and Engineering Lecture 6 Divide Floating Point Pentium Bug Recap of Last Lecture and Introduction of Today s Lecture 4 min Divide 20 min Questions and Administrative Matters 2 min Floating Point 25 min Questions and Break 5 min Pentium Bug 25min Feb 10 1999 John Kubiatowicz http cs berkeley edu kubitron lecture slides http www inst eecs berkeley edu cs152 2 10 99 UCB Spring 1999 CS152 Kubiatowicz Lec6 1 Recap of Last Lecture Summary 2 10 99 UCB Spring 1999 CS152 Kubiatowicz Lec6 2 Recap VHDL combinational example Intro to VHDL entity symbol architecture schematic signals wires behavior can be higher level x boolean expression A B C D ENTITY nandnor is GENERIC delay TIME 1ns PORT a b IN VLBIT x y OUT VLBIT END nandnore On line Design Notebook Open a window with editor or our tool cut paste ARCHITECTURE behavioral OF nandnor is Multiply successive refinement to see final design 32 bit Adder 64 bit shift register 32 bit Multiplicand Register Booth s algorithm to handle signed multiplies There are algorithms that calculate many bits of multiply per cycle see exercises 4 36 to 4 39 in COD BEGIN x a NOR b AFTER delay y a NAND x AFTER delay END behavioral Shifter Best implemented with technology specific methodologies What s Missing from MIPS is Divide Floating Point Arithmetic Next time the Pentium Bug 2 10 99 UCB Spring 1999 CS152 Kubiatowicz Lec6 3 2 10 99 UCB Spring 1999 CS152 Kubiatowicz Lec6 4 Review MULTIPLY HARDWARE Version 3 Review Booth s Algorithm Insight middle of run end of run 32 bit Multiplicand reg 32 bit ALU 64 bit Product reg shift right 0 bit Multiplier reg 011110 Current Bit Bit to the Right Multiplicand 32 bits beginning of run Explanation Example Op 1 0 Begins run of 1s 0001111000 sub 1 1 Middle of run of 1s 0001111000 none 0 1 End of run of 1s 0001111000 add 0 0 Middle of run of 0s 0001111000 none 32 bit ALU HI LO Shift Right Product Multiplier Write 64 bits 2 10 99 Originally for Speed when shift was faster than add Control CS152 Kubiatowicz Lec6 5 UCB Spring 1999 Radix 4 Modified Booth s Algorithm Current Bits Bit to the Right Explanation 1 10000 01111 Replace a string of 1s in multiplier with an initial subtract when we first see a one and then later add for the bit after the last one Example 2 10 99 CS152 Kubiatowicz Lec6 6 UCB Spring 1999 Review Combinational Shifter from MUXes Basic Building Block Recode sel A B 1 0 00 0 Middle of zeros 00 00 00 00 00 0 01 0 Single one 00 00 00 01 00 1 10 0 Begins run of 1s 00 01 11 10 00 2 11 0 Begins run of 1s 00 01 11 11 00 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 00 1 Ends run of 1s 00 00 11 11 00 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 01 1 Ends run of 1s 00 01 11 11 00 2 10 1 Isolated 0 00 11 10 11 00 1 11 1 Middle of run 00 11 11 11 00 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 A7 R7 1 10000 01111 Same insight as one bit Booth s simply adjust for alignment of 2 bits Allows multiplication 2 bits at a time 2 10 99 UCB Spring 1999 CS152 Kubiatowicz Lec6 7 D 8 bit right shifter A6 R6 A5 R5 A4 R4 A3 R3 A2 R2 A1 R1 S2 S1 S0 A0 R0 What comes in the MSBs How many levels for 32 bit shifter What if we use 4 1 Muxes 2 10 99 UCB Spring 1999 CS152 Kubiatowicz Lec6 8 Funnel Shifter Barrel Shifter Technology dependent solutions transistor per switch Instead Extract 32 bits of 64 SR3 Y SR2 SR1 SR0 X D3 Shift Right D2 A6 Shift A by i bits sa shift right amount Logical Y 0 R Y 32 X A sa i D1 X 32 A5 Arithmetic Y Sign X A sa i D0 Shift Right Rotate Y A Left shifts Y A A4 X A sa i 32 X 0 sa 32 i 2 10 99 R UCB Spring 1999 A3 CS152 Kubiatowicz Lec6 9 Divide Paper Pencil 1001 Divisor 1000 1001010 1000 10 101 1010 1000 10 A2 2 10 99 A1 A0 CS152 Kubiatowicz Lec6 10 UCB Spring 1999 DIVIDE HARDWARE Version 1 Quotient 64 bit Divisor reg 64 bit ALU 64 bit Remainder reg 32 bit Quotient reg Dividend Shift Right Divisor 64 bits Remainder or Modulo result Quotient 64 bit ALU Shift Left 32 bits See how big a number can be subtracted creating quotient bit on each step Remainder Binary 1 divisor or 0 divisor Write Control 64 bits Dividend Quotient x Divisor Remainder Dividend Quotient Divisor 3 versions of divide successive refinement 2 10 99 UCB Spring 1999 CS152 Kubiatowicz Lec6 11 2 10 99 UCB Spring 1999 CS152 Kubiatowicz Lec6 12 Divide Algorithm Version 1 Takes n 1 steps for n bit Quotient Rem Remainder Quotient Divisor 0000 0111 0000 0010 0000 Start Place Dividend in Remainder 1 Subtract the Divisor register from the Remainder register and place the result in the Remainder register Remainder 0 Test Remainder Remainder 0 2b Restore the original value by adding the Divisor register to the Remainder register place the sum in the Remainder register Also shift the Quotient register to the left setting the new least significant bit to 0 2a Shift the Quotient register to the left setting the new rightmost bit to 1 3 Shift the Divisor register right1 bit n 1 repetition Observations on Divide Version 1 1 2 bits in divisor always 0 1 2 of 64 bit adder is wasted 1 2 of divisor is wasted Instead of shifting divisor to right shift remainder to left 1st step cannot produce a 1 in quotient bit otherwise too big switch order to shift first and then subtract can save 1 iteration No n 1 repetitions Yes n 1 repetitions n 4 here 2 10 99 UCB Done Spring 1999 CS152 Kubiatowicz Lec6 13 Divide Paper Pencil Divisor 0001 2 10 99 DIVIDE HARDWARE Version 2 01010 Quotient 00001010 00001 0001 0000 0001 0001 0 00 Dividend 32 bit Divisor reg 32 bit ALU 64 bit Remainder reg 32 bit Quotient reg Divisor 32 bits Remainder or Modulo result Quotient 32 bit ALU Notice that there is no way to get a 1 in leading digit this would be an overflow since quotient would have n 1 bits 2 10 99 CS152 Kubiatowicz Lec6 14 UCB Spring 1999 UCB Spring 1999 CS152 Kubiatowicz Lec6 15 Shift Left 32 bits Shift Left Remainder 64 bits 2 10 99 Control Write UCB Spring 1999 CS152 Kubiatowicz Lec6 16 Divide Algorithm Version 2 Remainder Quotient Divisor 0000 0111 0000 Start Place Dividend in …
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