1/25/99 ©UCB Spring 1999CS152KubiatowiczLec2.1January 25, 1999John Kubiatowicz (http.cs.berkeley.edu/~kubitron)lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/CS152Computer Architecture and EngineeringLecture 2Review of MIPS ISA and Performance1/25/99 ©UCB Spring 1999CS152 / KubiatowiczLec2.2Overview of Today’s Lecture: Review Instruction Sets, Performance Review from Last Lecture (1 min) Classes, Addressing, Format (20 min) Administrative Matters (3 min) Operations, Branching, Calling conventions (25 min) Break (5 min) MIPS Details, Performance (25 min)1/25/99 ©UCB Spring 1999CS152 / KubiatowiczLec2.3Review: Organization All computers consist of five components• Processor: (1) datapath and (2) control• (3) Memory• I/O: (4) Input devices and (5) Output devices Not all “memory” is created equally• Cache: fast (expensive) memory are placed closer tothe processor• Main memory: less expensive memory--we can havemore Input and output (I/O) devices have the messiestorganization• Wide range of speed: graphics vs. keyboard• Wide range of requirements: speed, standard, cost ...• Least amount of research (so far)1/25/99 ©UCB Spring 1999CS152 / KubiatowiczLec2.4Summary: Computer System ComponentsProcCachesBussesMemoryI/O Devices:ControllersadaptersDisksDisplaysKeyboardsNetworks All have interfaces & organizations1/25/99 ©UCB Spring 1999CS152 / KubiatowiczLec2.5Review: Instruction Set Designinstruction setsoftwarehardware1/25/99 ©UCB Spring 1999CS152 / KubiatowiczLec2.6Instruction Set Architecture: What Must be Specified?InstructionFetchInstructionDecodeOperandFetchExecuteResultStoreNextInstruction Instruction Format or Encoding• how is it decoded? Location of operands and result• where other than memory?• how many explicit operands?• how are memory operands located?• which can or cannot be in memory? Data type and Size Operations• what are supported Successor instruction• jumps, conditions, branches•fetch-decode-execute is implicit!1/25/99 ©UCB Spring 1999CS152 / KubiatowiczLec2.7Basic ISA ClassesAccumulator (1 register):1 addressadd Aacc ← acc + mem[A]1+x address addx A acc ← acc + mem[A + x]Stack:0 address add tos ← tos + nextGeneral Purpose Register (can be memory/memory):2 address add A B EA[A] ← EA[A] + EA[B]3 address add A B C EA[A] ← ΕΑ[B] + EA[C]Load/Store:3 address add Ra Rb Rc Ra ← Rb + Rcload Ra Rb Ra ← mem[Rb]store Ra Rb mem[Rb] ← RaComparison:Bytes per instruction? Number of Instructions? Cycles per instruction?Most real machines are hybrids of these.1/25/99 ©UCB Spring 1999CS152 / KubiatowiczLec2.8Comparing Number of InstructionsCode sequence for (C = A + B) for four classes of instruction StackAccumulatorRegister (load-store)Push A Load A Load R1,APush B Add B Load R2,BAdd Store CRegister (register-memory)Load R1,AAdd R1,BStore C, R1 Add R3,R1,R2Pop C Store C,R31/25/99 ©UCB Spring 1999CS152 / KubiatowiczLec2.9General Purpose Registers Dominate° 1975-1998 all machines use general purpose registers° Advantages of registers• registers are faster than memory• registers are easier for a compiler to use-e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order vs. stack• registers can hold variables- memory traffic is reduced, so program is sped up (since registers are faster than memory)-code density improves (since register named with fewer bits than memory location)1/25/99 ©UCB Spring 1999CS152 / KubiatowiczLec2.10MIPS I Registers Programmable storage• 2^32 x bytes of memory• 31 x 32-bit GPRs (R0 = 0)• 32 x 32-bit FP regs (paired DP)• HI, LO, PC0r0r1°°°r31PClohi1/25/99 ©UCB Spring 1999CS152 / KubiatowiczLec2.11Memory Addressing° Since 1980 almost every machine uses addresses to level of 8-bits (byte)° 2 questions for design of ISA:• Since could read a 32-bit word as four loads of bytes from sequential byte addresses or as one load word from a single byte address, How do byte addresses map onto words?• Can a word be placed on any byte boundary?1/25/99 ©UCB Spring 1999CS152 / KubiatowiczLec2.12Addressing Objects: Endianess and Alignment Big Endian: address of most significant byte = word address(xx00 = Big End of word)• IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA Little Endian:address of least significant byte = word address(xx00 = Little End of word)• Intel 80x86, DEC Vax, DEC Alpha (Windows NT)msblsb3 2 1 0little endian byte 00 1 2 3big endian byte 0Alignment: require that objects fall on address that is multiple of their size.0 1 2 3AlignedNotAligned1/25/99 ©UCB Spring 1999CS152 / KubiatowiczLec2.13Addressing ModesAddressing mode Example MeaningRegister Add R4,R3R4← R4+R3Immediate Add R4,#3R4 ← R4+3Displacement Add R4,100(R1)R4 ← R4+Mem[100+R1]Register indirect Add R4,(R1)R4 ← R4+Mem[R1]Indexed / Base Add R3,(R1+R2)R3 ← R3+Mem[R1+R2]Direct or absolute Add R1,(1001)R1 ← R1+Mem[1001]Memory indirect Add R1,@(R3)R1 ← R1+Mem[Mem[R3]]Post-increment Add R1,(R2)+ R1 ← R1+Mem[R2]; R2 ← R2+dPre-decrement Add R1,–(R2)R2 ← R2–d; R1 ← R1+Mem[R2]Scaled Add R1,100(R2)[R3]R1 ← R1+Mem[100+R2+R3*d]Why Post-increment/Pre-decrement? Scaled?1/25/99 ©UCB Spring 1999CS152 / KubiatowiczLec2.14Addressing Mode Usage? (ignore register mode)3 programs measured on machine with all address modes (VAX)--- Displacement: 42% avg, 32% to 55% 75%--- Immediate: 33% avg, 17% to 43% 85%--- Register deferred (indirect): 13% avg, 3% to 24%--- Scaled: 7% avg, 0% to 16%--- Memory indirect: 3% avg, 1% to 6% --- Misc: 2% avg, 0% to 3%75% displacement & immediate88% displacement, immediate & register indirect1/25/99 ©UCB Spring 1999CS152 / KubiatowiczLec2.15Displacement Address Size?° Avg. of 5 SPECint92 programs v. avg. 5 SPECfp92 programs ° 1% of addresses > 16-bits° 12 - 16 bits of displacement needed0%10%20%30%0123456789101112131415Int. Avg. FP Avg.Address Bits1/25/99 ©UCB Spring 1999CS152 / KubiatowiczLec2.16Immediate Size?• 50% to 60% fit within 8 bits• 75% to 80% fit within 16 bits1/25/99 ©UCB Spring 1999CS152 / KubiatowiczLec2.17Addressing Summary• Data Addressing modes that are important:Displacement, Immediate, Register Indirect• Displacement size should be 12 to 16 bits• Immediate size should be 8 to 16 bits1/25/99 ©UCB Spring
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