Overview of Today s Lecture Review Instruction Sets Performance CS152 Computer Architecture and Engineering Lecture 2 Review of MIPS ISA and Performance Review from Last Lecture 1 min Classes Addressing Format 20 min Administrative Matters 3 min Operations Branching Calling conventions 25 min January 25 1999 John Kubiatowicz http cs berkeley edu kubitron Break 5 min MIPS Details Performance 25 min lecture slides http www inst eecs berkeley edu cs152 1 25 99 UCB Spring 1999 CS152Kubiatowicz Lec2 1 Review Organization 1 25 99 Summary Computer System Components All computers consist of five components Processor 1 datapath and 2 control 3 Memory I O 4 Input devices and 5 Output devices Proc Caches Busses Not all memory is created equally Cache fast expensive memory are placed closer to the processor Main memory less expensive memory we can have more Input and output I O devices have the messiest organization Wide range of speed graphics vs keyboard Wide range of requirements speed standard cost Least amount of research so far 1 25 99 UCB Spring 1999 CS152 Kubiatowicz Lec2 2 UCB Spring 1999 CS152 Kubiatowicz Lec2 3 adapters Memory Controllers I O Devices Disks Displays Keyboards Networks All have interfaces organizations 1 25 99 UCB Spring 1999 CS152 Kubiatowicz Lec2 4 Instruction Set Architecture What Must be Specified Review Instruction Set Design Instruction Fetch Instruction Decode software Operand Fetch instruction set Execute hardware Instruction Format or Encoding how is it decoded Location of operands and result where other than memory how many explicit operands how are memory operands located which can or cannot be in memory Data type and Size Operations what are supported Result Store Successor instruction Next Instruction 1 25 99 UCB Spring 1999 Basic ISA Classes CS152 Kubiatowicz Lec2 5 Most real machines are hybrids of these Accumulator 1 register 1 address add A acc acc mem A 1 x address addx A acc acc mem A x tos tos next add General Purpose Register can be memory memory 2 address add A B 3 address add A B C UCB Spring 1999 CS152 Kubiatowicz Lec2 6 Comparing Number of Instructions Code sequence for C A B for four classes of instruction Stack 0 address 1 25 99 jumps conditions branches fetch decode execute is implicit EA A EA A EA B EA A B EA C Register register memory Register load store Stack Accumulator Push A Load A Load R1 A Load R1 A Push B Add B Add R1 B Load R2 B Add Store C Store C R1 Pop C Add R3 R1 R2 Store C R3 Load Store 3 address add Ra Rb Rc Ra Rb Rc load Ra Rb Ra mem Rb store Ra Rb mem Rb Ra Comparison Bytes per instruction Number of Instructions Cycles per instruction 1 25 99 UCB Spring 1999 CS152 Kubiatowicz Lec2 7 1 25 99 UCB Spring 1999 CS152 Kubiatowicz Lec2 8 General Purpose Registers Dominate MIPS I Registers Programmable storage 2 32 x bytes of memory 1975 1998 all machines use general purpose registers Advantages of registers registers are faster than memory registers are easier for a compiler to use e g A B C D E F can do multiplies in any order vs stack 31 x 32 bit GPRs R0 0 32 x 32 bit FP regs paired DP HI LO PC r0 r1 r31 PC lo hi 0 registers can hold variables memory traffic is reduced so program is sped up since registers are faster than memory code density improves since register named with fewer bits than memory location 1 25 99 UCB Spring 1999 CS152 Kubiatowicz Lec2 9 Memory Addressing 1 25 99 CS152 Kubiatowicz Lec2 10 UCB Spring 1999 Addressing Objects Endianess and Alignment Since 1980 almost every machine uses addresses to level of 8 bits byte 2 questions for design of ISA Since could read a 32 bit word as four loads of bytes from sequential byte addresses or as one load word from a single byte address How do byte addresses map onto words Big Endian address of most significant byte word address xx00 Big End of word IBM 360 370 Motorola 68k MIPS Sparc HP PA Little Endian address of least significant byte word address xx00 Little End of word Intel 80x86 DEC Vax DEC Alpha Windows NT little endian byte 0 3 Can a word be placed on any byte boundary 2 1 0 lsb msb 0 0 big endian byte 0 1 2 1 2 3 3 Aligned Alignment require that objects fall on address that is multiple of their size Not Aligned 1 25 99 UCB Spring 1999 CS152 Kubiatowicz Lec2 11 1 25 99 UCB Spring 1999 CS152 Kubiatowicz Lec2 12 Addressing Modes Addressing Mode Usage ignore register mode Addressing mode Example Meaning 3 programs measured on machine with all address modes VAX Register Add R4 R3 R4 R4 R3 Displacement 42 avg 32 to 55 Immediate Add R4 3 R4 R4 3 Immediate 33 avg 17 to 43 Displacement Add R4 100 R1 R4 R4 Mem 100 R1 Register indirect Add R4 R1 Indexed Base Add R3 R1 R2 R3 R3 Mem R1 R2 Direct or absolute Add R1 1001 R1 R1 Mem 1001 Memory indirect Add R1 R3 R1 R1 Mem Mem R3 Post increment Add R1 R2 R1 R1 Mem R2 R2 R2 d Pre decrement Add R1 R2 R2 R2 d R1 R1 Mem R2 Scaled Scaled 7 avg 0 to 16 Memory indirect 3 avg 1 to 6 Misc 2 avg 0 to 3 75 displacement immediate 88 displacement immediate register indirect R1 R1 Mem 100 R2 R3 d Why Post increment Pre decrement Scaled 1 25 99 85 Register deferred indirect 13 avg 3 to 24 R4 R4 Mem R1 Add R1 100 R2 R3 75 UCB Spring 1999 CS152 Kubiatowicz Lec2 13 Displacement Address Size 1 25 99 UCB Spring 1999 CS152 Kubiatowicz Lec2 14 Immediate Size Int Avg FP Avg 50 to 60 fit within 8 bits 30 75 to 80 fit within 16 bits 20 10 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 Address Bits Avg of 5 SPECint92 programs v avg 5 SPECfp92 programs 1 of addresses 16 bits 12 16 bits of displacement needed 1 25 99 UCB Spring 1999 CS152 Kubiatowicz Lec2 15 1 25 99 UCB Spring 1999 CS152 Kubiatowicz Lec2 16 Addressing Summary Generic Examples of Instruction Format Widths Data Addressing modes that are important Displacement Immediate Register Indirect Variable Displacement size should be 12 to 16 bits Fixed Immediate size should be 8 to 16 bits Hybrid 1 25 99 UCB Spring 1999 CS152 Kubiatowicz Lec2 17 Instruction Formats 1 25 99 UCB Spring 1999 CS152 Kubiatowicz Lec2 18 Instruction Format If code size is most important use variable length instructions If have many memory operands per instruction and or many addressing modes Need one address specifier per operand If performance is most important use fixed length instructions Recent embedded machines ARM MIPS added optional mode to execute subset of 16 bit wide instructions Thumb MIPS16 per procedure decide performance or density If have load store machine with 1 …
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