EECS150 Digital Design Lecture 10 Timing February 20 2003 John Wawrzynek Spring 2003 EECS150 Lec10 Timing Page 1 Outline General Model of Synchronous Systems Performance Limits Delay in logic gates Delay in wires Clock Skew Delay in flip flops Spring 2003 EECS150 Lec10 Timing Page 2 General Model of Synchronous Circuit clock input input CL CL reg reg output option feedback output All wires except clock may be multiple bits wide Registers reg collections of flip flops clock distributed to all flip flops Combinational Logic Blocks CL no internal state output only a function of inputs Particular inputs outputs are optional Optional Feedback typical rate Spring 2003 EECS150 Lec10 Timing Page 3 Example Circuit Parallel to Serial Converter Spring 2003 All signal paths single bit wide Registers are single flip flops Combinational Logic blocks are simple multiplexors No feedback in this case EECS150 Lec10 Timing Page 4 General Model of Synchronous Circuit clock input input CL reg CL reg output option feedback output How do we measure performance operations sec cycles sec What limits the clock rate What happens as we increase the clock rate Spring 2003 EECS150 Lec10 Timing Page 5 Limitations on Clock Rate 1 Logic Gate Delay 2 Delays in flip flops D input clk output Q t What are typical delay values setup time clock to Q delay Both times contribute to limiting the clock period What must happen in one clock cycle for correct operation Assuming perfect clock distribution all flip flops see the clock at the same time All signals must be ready and setup before rising edge of clock Spring 2003 EECS150 Lec10 Timing Page 6 Example Parallel to serial converter clk a b T time clk Q time mux time setup T clk Q mux setup Spring 2003 EECS150 Lec10 Timing Page 7 General Model of Synchronous Circuit clock input input CL CL reg reg output option feedback output In general for correct operation T time clk Q time CL time setup T clk Q CL setup for all paths How do we enumerate all paths Any circuit input or register output to any register input or circuit output setup time for circuit outputs depends on what it connects to clk Q time for circuit inputs depends on from where it comes Spring 2003 EECS150 Lec10 Timing Page 8 Qualitative Analysis of Logic Delay Improved Transistor Model nFET We refer to transistor strength as the amount of current that flows for a given Vds and Vgs The strength is linearly proportional to the ratio of W L pFET Spring 2003 EECS150 Lec10 Timing Page 9 Gate Switching Behavior Inverter NAND gate Spring 2003 EECS150 Lec10 Timing Page 10 Gate Delay Cascaded gates Vout Vin Spring 2003 EECS150 Lec10 Timing Page 11 Gate Delay Fan out 2 1 3 The delay of a gate is proportional to its output capacitance Because gates 2 and 3 turn on off at a later time It takes longer for the output of gate 1 to reach the switching threshold of gates 2 and 3 as we add more output capacitance Spring 2003 EECS150 Lec10 Timing Page 12 Gate Delay Fan in What is the delay in this circuit Critical Path the path with the maximum delay from any input to any output In general we include register set up and clk to Q times in critical path calculation Why do we care about the critical path Spring 2003 EECS150 Lec10 Timing Page 13 Delay in Flip flops D Setup time results from delay through first latch clk clk Q clk setup time clock to Q delay clk clk Clock to Q delay results from delay through second latch clk clk clk clk Spring 2003 EECS150 Lec10 Timing Page 14 Wire Delay In general wire behave as transmission lines signal wave front moves close to the speed of light 1ft ns Time from source to destination is called the transit time In ICs most wires are short and the transit times are relatively short compared to the clock period and can be ignored Not so on PC boards t x Spring 2003 EECS150 Lec10 Timing Page 15 Wire Delay Even in those cases where the transmission line effect is negligible Wires posses distributed resistance and capacitance v1 v2 v3 v4 v1 v2 v3 Typically around half of C of gate load is in the wires Time constant associated with distributed RC is proportional to the square of the length For short wires on ICs resistance is insignificant relative to effective R of transistors but C is important For long wires on ICs busses clock lines global control signal etc Resistance is significant therefore distributed RC effect dominates signals are typically rebuffered to reduce delay v4 time Spring 2003 EECS150 Lec10 Timing Page 16 Clock Skew Unequal delay in distribution of the clock signal to various parts of a circuit if not accounted for can lead to erroneous behavior Comes about because clock wires have delay circuit is designed with a different number of clock buffers from the clock source to the various clock loads or buffers have unequal delay All synchronous circuits experience some clock skew more of an issue for high performance designs operating with very little extra time per clock cycle clock skew delay in distribution Spring 2003 EECS150 Lec10 Timing Page 17 CLK CLK Clock Skew cont CLK CL CLK clock skew delay in distribution If clock period T TCL Tsetup Tclk Q circuit will fail Therefore 1 Control clock skew a Careful clock distribution Equalize path delay from clock source to all clock loads by controlling wires delay and buffer delay b don t gate clocks 2 T TCL Tsetup Tclk Q worst case skew Most modern large high performance chips microprocessors control end to end clock skew to a few tenths of a nanosecond Spring 2003 EECS150 Lec10 Timing Page 18 CLK CLK Clock Skew cont CLK CL CLK clock skew delay in distribution Note reversed buffer In this case clock skew actually provides extra time adds to the effective clock period This effect has been used to help run circuits as higher clock rates Risky business Spring 2003 EECS150 Lec10 Timing Page 19
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