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Berkeley COMPSCI 152 - Lecture 10 - Timing

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Spring 2003 EECS150 – Lec10-TimingPage 1EECS150 - Digital DesignLecture 10 - TimingFebruary 20, 2003John WawrzynekSpring 2003 EECS150 – Lec10-TimingPage 2Outline• General Model of Synchronous Systems– Performance Limits• Delay in logic gates•Delay in wires•Clock Skew• Delay in flip-flopsSpring 2003 EECS150 – Lec10-TimingPage 3General Model of Synchronous Circuit• All wires, except clock, may be multiple bits wide.• Registers (reg)– collections of flip-flops•clock– distributed to all flip-flops– typical rate?• Combinational Logic Blocks (CL)– no internal state– output only a function of inputs• Particular inputs/outputs are optional• Optional Feedbackreg regCL CLclock inputoutputoption feedbackinputoutputSpring 2003 EECS150 – Lec10-TimingPage 4Example Circuit• Parallel to Serial Converter• All signal paths single bit wide• Registers are single flip-flops• Combinational Logic blocks are simple multiplexors• No feedback in this case.Spring 2003 EECS150 – Lec10-TimingPage 5General Model of Synchronous Circuit• How do we measure performance?– operations/sec?– cycles/sec?• What limits the clock rate?• What happens as we increase the clock rate?reg regCL CLclock inputoutputoption feedbackinputoutputSpring 2003 EECS150 – Lec10-TimingPage 6Limitations on Clock Rate1 Logic Gate Delay• What are typical delay values?2 Delays in flip-flops• Both times contribute to limiting the clock period.tinputoutputDclkQsetup time clock to Q delay• What must happen in one clock cycle for correct operation?• Assuming perfect clock distribution (all flip-flops see the clock at the same time):– All signals must be ready and “setup” before rising edge of clock.Spring 2003 EECS150 – Lec10-TimingPage 7Example• Parallel to serial converter: abT ≥ time(clk→Q) + time(mux) + time(setup)T ≥τclk→Q+ τmux+ τsetupclkSpring 2003 EECS150 – Lec10-TimingPage 8General Model of Synchronous Circuit• In general, for correct operation:for all paths.• How do we enumerate all paths?– Any circuit input or register output to any register input or circuit output.– “setup time” for circuit outputs depends on what it connects to– “clk-Q time” for circuit inputs depends on from where it comes.reg regCL CLclock inputoutputoption feedbackinputoutputT ≥ time(clk→Q) + time(CL) + time(setup)T ≥τclk→Q+ τCL+ τsetupSpring 2003 EECS150 – Lec10-TimingPage 9Qualitative Analysis of Logic Delay• Improved Transistor Model: nFET• We refer to transistor "strength" as the amount of current that flows for a given Vds and Vgs. • The strength is linearly proportional to the ratio of W/L. pFETSpring 2003 EECS150 – Lec10-TimingPage 10Gate Switching Behavior• Inverter:• NAND gate:Spring 2003 EECS150 – Lec10-TimingPage 11Gate Delay• Cascaded gates:VoutVinSpring 2003 EECS150 – Lec10-TimingPage 12Gate Delay• Fan-out:• The delay of a gate is proportional to its output capacitance. Because, gates #2 and 3 turn on/off at a later time. (It takes longer for the output of gate #1 to reach the switching threshold of gates #2 and 3 as we add more output capacitance.)132Spring 2003 EECS150 – Lec10-TimingPage 13Gate Delay• “Fan-in”• What is the delay in this circuit?• Critical Path: the path with the maximum delay, from any input to any output.– In general, we include register set-up and clk-to-Q times in critical path calculation.• Why do we care about the critical path?Spring 2003 EECS150 – Lec10-TimingPage 14Delay in Flip-flops• Setup time results from delay through first latch.• Clock to Q delay results from delay through second latch.DclkQsetup time clock to Q delayclkclk’clkclkclk’clk’clkclk’Spring 2003 EECS150 – Lec10-TimingPage 15Wire Delay• In general, wire behave as “transmission lines”:– signal wave-front moves close to the speed of light• ~1ft/ns– Time from source to destination is called the “transit time”.– In ICs most wires are short, and the transit times are relatively short compared to the clock period and can be ignored.– Not so on PC boards.txSpring 2003 EECS150 – Lec10-TimingPage 16Wire Delay• Even in those cases where the transmission line effect is negligible:– Wires posses distributed resistance and capacitance– Time constant associated with distributed RC is proportional to the square of the length•For short wires on ICs, resistance is insignificant (relative to effective R of transistors), but C is important.– Typically around half of C of gate load is in the wires.•For long wires on ICs:– busses, clock lines, global control signal, etc.– Resistance is significant, therefore distributed RC effect dominates.– signals are typically “rebuffered” to reduce delay:v1v4v3v2timev1 v2 v3 v4Spring 2003 EECS150 – Lec10-TimingPage 17Clock Skew• Unequal delay in distribution of the clock signal to various parts of a circuit:– if not accounted for, can lead to erroneous behavior.– Comes about because:• clock wires have delay,• circuit is designed with a different number of clock buffers from the clock source to the various clock loads, or• buffers have unequal delay.– All synchronous circuits experience some clock skew:• more of an issue for high-performance designs operating with very little extra time per clock cycle.clock skew, delay in distributionSpring 2003 EECS150 – Lec10-TimingPage 18Clock Skew (cont.)• If clock period T = TCL+Tsetup+Tclk→Q, circuit will fail.• Therefore:1. Control clock skewa) Careful clock distribution. Equalize path delay from clock source to all clock loads by controlling wires delay and buffer delay.b) don’t “gate” clocks.2. T ≥ TCL+Tsetup+Tclk→Q + worst case skew.• Most modern large high-performance chips (microprocessors) control end to end clock skew to a few tenths of a nanosecond.clock skew, delay in distributionCLCLKCLK’CLKCLK’Spring 2003 EECS150 – Lec10-TimingPage 19Clock Skew (cont.)• Note reversed buffer.• In this case, clock skew actually provides extra time (adds to the effective clock period).• This effect has been used to help run circuits as higher clock rates. Risky business!CLCLKCLK’clock skew, delay in


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Berkeley COMPSCI 152 - Lecture 10 - Timing

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