PowerPoint PresentationReviewOutlineHow to Design a Processor: step-by-stepThe MIPS Instruction FormatsStep 1a: The MIPS-lite Subset for todayLectures vs. Chapter 5 COD 3/eUsing Hardware Description Lang.Step 1: Requirements of the Instruction SetStep 2: Components of the DatapathCombinational Logic Elements (Basic Building Blocks)Storage Element: Register (Basic Building Block)Storage Element: Register FileStorage Element: Idealized MemoryAdministriviaComputers In The NewsReview: Clocking MethodologyStep 3: Assemble Datapath meeting our requirements3a: Overview of the Instruction Fetch Unit3b: Add & SubtractRegister-Register Timing: One complete cycle3c: Logical Operations with Immediate3d: Load Operations3e: Store Operations3f: The Branch InstructionDatapath for Branch OperationsPutting it All Together: A Single Cycle DatapathLectures vs. Chapter 5 3/eStep 5: Implement the controlTypes of Bugs in Single Cycle Lab 2?Recap Test Plan: The testing timelinePeer Evaluation Question AssumptionsPeer Instruction: What is critical path for BEQ?Peer Instruction: What is critical path for LW?Peer Instruction: Which has longest critical path?An Abstract View of the ImplementationWhy should you keep a design notebook?Why do we keep it on-line?How should you do it?On-line Notebook Example1st page of On-line notebook (Index + Wed. 9/6/95)2nd page of On-line notebook (Thursday 9/7/95)3rd page of On-line notebook (Monday 9/11/95)4th page of On-line notebook (9/11/95 contd)5th page of On-line notebook (9/11/95 contd)Added benefit: cool post-design statisticsLecture SummaryCS 152 L06 Single Cycle 1 (1)UC Regents Fall 2004 © UCB2004-09-16John Lazzaro(www.cs.berkeley.edu/~lazzaro)Dave Patterson (www.cs.berkeley.edu/~patterson) www-inst.eecs.berkeley.edu/~cs152/CS152 – Computer Architecture andEngineeringLecture 6 – Single Cycle + Design NotebookCS 152 L06 Single Cycle 1 (2)UC Regents Fall 2004 © UCBReviewXilinx: Physical, yet configurableTiming key concept: critical pathCS 152 L06 Single Cycle 1 (3)UC Regents Fall 2004 © UCBOutline°Single clock cycle per instruction=> Data path resource used at most once per instruction=> Need to replicate some data path resources if need more than once: memory, ALU/adders, …°Timing, Testing of Single Cycle°Single Cycle Datapath•5 generic steps (on next slide)•See how far we get this lecture; finish next time°Design NotebookCS 152 L06 Single Cycle 1 (4)UC Regents Fall 2004 © UCBHow to Design a Processor: step-by-step°1. Analyze instruction set => datapath requirements•the meaning of each instruction is given by the register transfers•datapath must include storage element for ISA registers-possibly more•datapath must support each register transfer°2. Select set of datapath components and establish clocking methodology°3. Assemble datapath meeting the requirements°4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.°5. Assemble the control logicCS 152 L06 Single Cycle 1 (5)UC Regents Fall 2004 © UCBThe MIPS Instruction Formats°All MIPS instructions are 32 bits long. The three instruction formats:•R-type•I-type•J-type°The different fields are:•op: operation of the instruction•rs, rt, rd: the source and destination register specifiers•shamt: shift amount•funct: selects the variant of the operation in the “op” field•address / immediate: address offset or immediate value•target address: target address of the jump instruction op target address026316 bits 26 bitsop rs rt rd shamt funct0611162126316 bits 6 bits5 bits5 bits5 bits5 bitsop rs rtimmediate0162126316 bits 16 bits5 bits5 bitsCS 152 L06 Single Cycle 1 (6)UC Regents Fall 2004 © UCBStep 1a: The MIPS-lite Subset for today°ADD and SUB•addU rd, rs, rt•subU rd, rs, rt°OR Immediate:•ori rt, rs, imm16°LOAD and STORE Word•lw rt, rs, imm16•sw rt, rs, imm16°BRANCH:•beq rs, rt, imm16op rs rt rd shamt funct0611162126316 bits 6 bits5 bits5 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsCS 152 L06 Single Cycle 1 (7)UC Regents Fall 2004 © UCBLectures vs. Chapter 5 COD 3/eLectures°MIPS-lite subset:•Addu, Subu, LW, SW•BEQ, ORiBook°MIPS-lite subset:•Add, Sub, LW, SW•BEQ, OR•AND, SLT, J°Difficult complaint for textbook author: Lecturing directly from the textbook!°Good news: These lectures differ from bookCS 152 L06 Single Cycle 1 (8)UC Regents Fall 2004 © UCBUsing Hardware Description Lang. °All start by fetching the instructionop | rs | rt | rd | shamt | funct <= MEM[ PC ]op | rs | rt | Imm16 <= MEM[ PC ]inst HDL descriptionADDU R[rd] <= R[rs] + R[rt]; PC <= PC + 4SUBU R[rd] <= R[rs] – R[rt]; PC <= PC + 4ORi R[rt] <= R[rs] | zero_ext(Imm16); PC <= PC + 4LOAD R[rt] <= MEM[ R[rs] + sign_ext(Imm16)]; PC <= PC + 4STORE MEM[ R[rs] + sign_ext(Imm16) ] <= R[rt]; PC <= PC + 4BEQ if ( R[rs] == R[rt] ) PC <= PC + 4 +{sign_ext(Imm16), 2’b00 } else PC <= PC + 4CS 152 L06 Single Cycle 1 (9)UC Regents Fall 2004 © UCBStep 1: Requirements of the Instruction Set°Memory•One for instructions, one for data°Registers (32 x 32bit)•Read RS•Read RT•Write RT or RD°PC°Sign Extender (for immediate field)°Add and Sub register or Extended Immediate°Add 4 or Extended Immediate to PCCS 152 L06 Single Cycle 1 (10)UC Regents Fall 2004 © UCBStep 2: Components of the Datapath°Combinational Logic Elements°Storage Elements (“State”)•Clocking methodologyCS 152 L06 Single Cycle 1 (11)UC Regents Fall 2004 © UCBCombinational Logic Elements (Basic Building Blocks)°Adder°MUX(multi-plexor)°ALU3232AB32SumCarry3232AB32ResultOP32AB32Y32SelectAdderMUXALUCarryIn(to add values)(to chose between values)(to do add, subtract, or)CS 152 L06 Single Cycle 1 (12)UC Regents Fall 2004 © UCBStorage Element: Register (Basic Building Block)°Register•Similar to the D Flip Flop except-N-bit input and output-Write Enable input•Write Enable:-negated (0): Data Out will not change-asserted (1): Data Out will become Data InClkData InWrite EnableN NData OutCS 152 L06 Single Cycle 1 (13)UC Regents Fall 2004 © UCBStorage Element: Register File°Register File consists of 32 registers:•Two 32-bit output busses: busA and busB•One 32-bit input bus: busW°Register is selected by:•RA (number) selects the register to put on busA (data)•RB
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