CS152 Computer Architecture and Engineering Lecture 6 Verilog (finish) Multiply, Divide, ShiftReview from last timeVerilog subtlety: Blocking AssignmentsVerilog subtlety: Non-Blocking AssignmentsSequential Logic (Revisited: better scheduling)A final word on VerilogHow Program: FPGA Generic Design FlowIdealized FPGA Logic Block4-LUT ImplementationLUT as general logic gatePowerPoint PresentationSlide 12Slide 13Example Partition, Placement, and RouteSlide 15Virtex-E Configurable Logic Block (CLB)Slide 17Details of Virtex-E SliceSlide 19AdministriviaMIPS arithmetic instructionsMULTIPLY (unsigned)Unsigned Combinational MultiplierHow does it work?Carry Save addition of 4 integersUnisigned shift-add multiplier (version 1)Multiply Algorithm Version 1Observations on Multiply Version 1MULTIPLY HARDWARE Version 2How to think of this?Simply warp to let product move right...Multiply Algorithm Version 2Still more wasted space!Observations on Multiply Version 2MULTIPLY HARDWARE Version 3Multiply Algorithm Version 3Observations on Multiply Version 3Motivation for Booth’s AlgorithmBooth’s AlgorithmBooths Example (2 x 7)Booths Example (2 x -3)Radix-4 Modified Booth’s AlgorithmDivide: Paper & PencilDIVIDE HARDWARE Version 1Divide Algorithm Version 1Divide Algorithm I example (7 / 2)Slide 47Observations on Divide Version 1Divide Algorithm I example: wasted spaceDIVIDE HARDWARE Version 2Divide Algorithm Version 2Observations on Divide Version 2DIVIDE HARDWARE Version 3Divide Algorithm Version 3Observations on Divide Version 3MIPS logical instructionsShiftersCombinational Shifter from MUXesGeneral Shift Right Scheme using 16 bit exampleFunnel ShifterBarrel ShifterSummaryTo Get More InformationCS152Computer Architecture and Engineering Lecture 6Verilog (finish)Multiply, Divide, ShiftFebruary 11, 2004John Kubiatowicz (www.cs.berkeley.edu/~kubitron)lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/2/11/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec6.2Review from last time°Design Process•Design Entry: Schematics, HDL, Compilers•High Level Analysis: Simulation, Testing, Assertions•Technology Mapping: Turn design into physical implementation•Low Level Analysis: Check out Timing, Setup/Hold, etc°Verilog – Three programming styles•Structural: Like a Netlist-Instantiation of modules + wires between them•Dataflow: Higher Level -Expressions instead of gates•Behavioral: Hardware programming-Full flow-control mechanisms-Registers, variables-File I/O, consol display, etc2/11/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec6.3°Blocking Assignments:•Assignments happen more like programming language (sequential code)•Both Right and left sides evaluated completely•Wait until assignment before going on-Can cause unexpected results when connecting output to logic in other always blocks.-Also a bit strange with delays on left hand side (LHS)°Example:reg E, C;always @(posedge clk)beginE = ~A;C = ~E;endAECVerilog subtlety: Blocking Assignments2/11/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec6.4°Non-blocking Assignments:•All right-hand sides evaluated immediately•Then assignments occur•If no delays, often want output ports to be assigned with non-blocking assignments°Example:reg E, C;always @(posedge clk)beginE <= ~A;C <= ~E;endA CEVerilog subtlety: Non-Blocking Assignments2/11/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec6.5Sequential Logic (Revisited: better scheduling)module FF (CLK,Q,D); input D, CLK; output Q; reg Q; always @ (posedge CLK) Q <= D;endmodule // FFGood: Doesn’t output until “after edge”Must be careful mixing zero-time blocking assignments and edge-triggering: Probably won’t do what you expect when connecting it to other things!module FF (CLK,Q,D); input D, CLK; output Q; reg Q; always @ (posedge CLK) Q = #5 D;endmodule // FFGood: Outputs 5 units “after edge”module FF (CLK,Q,D); input D, CLK; output Q; reg Q; always @ (posedge CLK) #5 Q = D;endmodule // FFProbably Not what you Expect:• Hold time of 5 units• glitches < 5 units ignored2/11/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec6.6A final word on Verilog°Verilog does not turn hardware design into writing programs!•Since Verilog looks similar to programming languages, some think that they can design hardware by writing programs.- NOT SO.•Verilog is a hardware description language. -The best way to use it is to first figure out the circuit you want, then figure out how to describe it in Verilog.•The behavioral construct hides a lot of the circuit details but you as the designer must still manage:- the structure-data-communication-Parallelism-timing of your design. -Not doing so leads to very inefficient designs!°Read the document on non-blocking assignment in Verilog that I put up on the handouts page. Lots of very interesting things!2/11/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec6.7How Program: FPGA Generic Design Flow°Design Entry:•Create your design files using:- schematic editor or -hardware description language (Verilog, VHDL)°Design “implementation” on FPGA:•Partition, place, and route (“PPR”) to create bit-stream file•Divide into CLB-sized pieces, place into blocks, route to blocks°Design verification:•Use Simulator to check function,•Other software determines max clock frequency.•Load onto FPGA device (cable connects PC to board)-check operation at full speed in real environment.2/11/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec6.8Idealized FPGA Logic Block°4-input Look Up Table (4-LUT)•implements combinational logic functions°Register•optionally stores output of LUT•Latch determines whether read reg or LUT4 - L U T F F10l a t c hL o g i c B l o c ks e t b y c o n f i g u r a t i o n b i t - s t r e a m4 - i n p u t " l o o k u p t a b l e "O U T P U TI N P U T S2/11/03 ©UCB Spring 2004CS152 / Kubiatowicz Lec6.94-LUT Implementation°n-bit LUT is actually implemented as a 2n x 1 memory:•inputs choose one of 2n memory locations.•memory locations (latches) are normally loaded with values from user’s configuration bit stream.•Inputs to mux control are the CLB (Configurable Logic Block) inputs.°Result is a general purpose “logic gate”. •n-LUT can implement any function of n inputs!l a t c hl a t c hl a t c hl a t c h1 6 x 1m u x1 6I N P U T SO U T P U TL a t c h e s p r o g r a m m e d a s p a r to f c o n f i g u r a t i o n b i t - s t r e a m2/11/03 ©UCB Spring 2004CS152 /
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