CS152 Computer Architecture and Engineering Lecture 6 Verilog finish Multiply Divide Shift February 11 2004 John Kubiatowicz www cs berkeley edu kubitron lecture slides http www inst eecs berkeley edu cs152 Review from last time Design Process Design Entry Schematics HDL Compilers High Level Analysis Simulation Testing Assertions Technology Mapping Turn design into physical implementation Low Level Analysis Check out Timing Setup Hold etc Verilog Three programming styles Structural Like a Netlist Instantiation of modules wires between them Dataflow Higher Level Expressions instead of gates Behavioral Hardware programming Full flow control mechanisms 2 11 03 Registers variables File I O consol display etc UCB Spring 2004 CS152 Kubiatowicz Verilog subtlety Blocking Assignments Blocking Assignments Assignments happen more like programming language sequential code Both Right and left sides evaluated completely Wait until assignment before going on Can cause unexpected results when connecting output to logic in other always blocks Also a bit strange with delays on left hand side LHS Example reg E C always posedge clk begin E A C E end E A 2 11 03 C UCB Spring 2004 CS152 Kubiatowicz Verilog subtlety Non Blocking Assignments Non blocking Assignments All right hand sides evaluated immediately Then assignments occur If no delays often want output ports to be assigned with non blocking assignments Example reg E C always posedge clk begin E A C E end E A 2 11 03 C UCB Spring 2004 CS152 Kubiatowicz Sequential Logic Revisited better scheduling Must be careful mixing zero time blocking assignments and edge triggering Probably won t do what you expect when connecting it to other things module FF CLK Q D input D CLK output Q reg Q always posedge CLK Q D endmodule FF Good Doesn t output until after edge Probably Not what you Expect Hold time of 5 units glitches 5 units ignored 2 11 03 module FF CLK Q D input D CLK output Q reg Q always posedge CLK Q 5 D endmodule FF Good Outputs 5 units after edge module FF CLK Q D input D CLK output Q reg Q always posedge CLK 5 Q D endmodule FF UCB Spring 2004 CS152 Kubiatowicz A final word on Verilog Verilog does not turn hardware design into writing programs Since Verilog looks similar to programming languages some think that they can design hardware by writing programs NOT SO Verilog is a hardware description language The best way to use it is to first figure out the circuit you want then figure out how to describe it in Verilog The behavioral construct hides a lot of the circuit details but you as the designer must still manage the structure data communication Parallelism timing of your design Not doing so leads to very inefficient designs Read the document on non blocking assignment in Verilog that I put up on the handouts page Lots of very interesting things 2 11 03 UCB Spring 2004 CS152 Kubiatowicz How Program FPGA Generic Design Flow Design Entry Create your design files using schematic editor or hardware description language Verilog VHDL Design implementation on FPGA Partition place and route PPR to create bit stream file Divide into CLB sized pieces place into blocks route to blocks Design verification Use Simulator to check function Other software determines max clock frequency Load onto FPGA device cable connects PC to board check operation at full speed in real environment 2 11 03 UCB Spring 2004 CS152 Kubiatowicz Idea lize d FP GA Log ic I N P U T S Blo ck L o g ic B lo c k la tc h s e t b y c o n f ig u r a t i o n b it s t r e a m 1 4 L U T FF OUTPUT 0 4 in p u t lo o k u p ta b le 4 input Look Up Table 4 LUT implements combinational logic functions Register optionally stores output of LUT Latch determines whether read reg or LUT 2 11 03 UCB Spring 2004 CS152 Kubiatowicz 4LUT Imp lem ent atiol a t c h n 2n x 1 memory inputs choose one of 2 n memory locations memory locations latches are normally loaded with values from user s configuration bit stream Inputs to mux control are the CLB Configurable Logic Block inputs IN P U T S la tc h 16 la tc h la tc h 2 11 03 16 x 1 m ux n bit LUT is actually implemented as a O U T P U T Result is a general purpose logic gate n LUT can implement any function of n inputs L a tc h e s p ro g ra m m e d a s p a rt o f c o n fig u r a tio n b it s tr e a m UCB Spring 2004 CS152 Kubiatowicz LUT as An n lut as a direct implementation of a gen truth table function eral Each latch location holds value of logi function corresponding to one input c combination gat e Example 2 lut IN P U T S 00 01 10 11 AND 0 0 0 1 OR 0 1 1 1 Implements any function of 2 inputs How many functions of n inputs 2 11 03 Example 4 lut IN P U T S 0000 0001 0010 0 0 11 0 0 11 0100 0101 0 11 0 0 11 1 1000 1001 1010 1 0 11 11 0 0 11 0 1 11 1 0 11 1 1 UCB Spring 2004 F 0 0 0 0 F 0 0 0 1 F 0 0 1 0 F 0 0 1 1 s to r e in 1 s t la t c h s to r e in 2 n d la t c h CS152 Kubiatowicz Additional application Distributed RAM RAM16X1S CLB LUT configurable as Distributed RAM A LUT equals 16x1 RAM LUT Implements Single and Dual Ports Cascade LUTs to increase RAM size O RAM32X1S D WE WCLK A0 A1 A2 A3 A4 Synchronous write Synchronous Asynchronous read Accompanying flip flops used for synchronous read D WE WCLK A0 A1 A2 A3 LUT LUT or O RAM16X2S D0 D1 WE WCLK A0 A1 A2 A3 O0 O1 or RAM16X1D D WE WCLK A0 SPO A1 A2 A3 DPRA0 DPO DPRA1 DPRA2 DPRA3 2 11 03 UCB Spring 2004 CS152 Kubiatowicz Block RAM Extra RAM not using LUTs Port B Port A Spartan IIE True Dual Port Block RAM Block RAM Most efficient memory implementation Dedicated blocks of memory Ideal for most memory requirements Virtex E XCV2000 has 160 blocks 4096 bits per blocks 4K x 1 2K x 4 512 x 8 256 x 16 Use multiple blocks for larger memories Builds both single and true dual port RAMs CORE Generator provides custom sized block RAMs Quickly generates optimized RAM implementation 2 11 03 UCB Spring 2004 CS152 Kubiatowicz Additional Application Shift Register Each LUT can be configured as shift register Serial in serial out LUT IN CE CLK Saves resources can use less than 16 FFs Faster no routing Note CAD tools determine with …
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