Slide 1Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38Slide 39Slide 40Slide 41Slide 42Slide 43Slide 44Slide 45Slide 46Slide 47Slide 48Slide 49Slide 50Slide 51Slide 52Slide 53Slide 54Slide 55Slide 56Slide 57Slide 58Slide 59Slide 60Slide 61Slide 62Slide 63Slide 64Slide 65Slide 66Slide 67Slide 68Slide 69Slide 70Slide 71Slide 72Slide 73Slide 74Slide 75Slide 76Slide 77Slide 78Slide 79Slide 80Slide 81Slide 82Slide 83Slide 84Slide 85Slide 86Slide 87Slide 88Slide 89Slide 90Slide 91Slide 92Slide 93Slide 94CS 152 L4: Testing and Teamwork UC Regents Fall 2006 © UCB2006-9-7John Lazzaro (www.cs.berkeley.edu/~lazzaro)CS 152 Computer Architecture and EngineeringLecture 4 – Testing and Teamworkwww-inst.eecs.berkeley.edu/~cs152/Congrats on Lab 1 !Congrats on Lab 1 !TAs: Udam Saini and Jue SunUC Regents Fall 2006 © UCBCS 152 L4: Testing and TeamworkLast Time: Single-Cycle Processors32rd1RegFile32rd2WE32wd5rs15rs25wsExtRegDestALUsrcExtOpALUctrMemToRegMemWrEqualRegWr32Addr DataInstrMemEqualRegDestRegWrExtOpALUsrcMemWrMemToRegPCSrcCombinational Logic(Only Gates, No Flip Flops)Just specify logic functions!UC Regents Fall 2006 © UCBCS 152 L4: Testing and TeamworkToday: Testing Processors + TeamworkUnit testing techniquesMaking a processor test planState machine testingTeamwork: Lessons learned from previous CS 152 classes.UC Regents Fall 2006 © UCBCS 152 L4: Testing and TeamworkLecture Focus: Functional Design Testtesting goalThe processor designcorrectly executes programs written in the supported subset of the MIPS ISAClock speed? CPI? Upcoming lectures ...Not manufacturing tests ...Intel XScale ARM Pipeline, IEEE Journal of Solid State Circuits, 36:11, November 2001CS 152 L4: Testing and Teamwork UC Regents Fall 2006 © UCBFour Types of TestingUC Regents Fall 2006 © UCBCS 152 L4: Testing and TeamworkBig Bang: Complete Processor TestingTop-downtestingBottom-uptestinghow it worksAssemble the complete processor.Execute test program suite on theprocessor.Check results.complete processor testing(Lab 1)This is how TAs test on checkoff days ...UC Regents Fall 2006 © UCBCS 152 L4: Testing and TeamworkMethodical Approach: Unit Testingcomplete processor testingWhat if the specification has a bug?Top-downtestingBottom-uptestingRemove a block from the design.Test it in isolation against specification.unit testinghow it worksWhat if team members do not use the exact same specification?UC Regents Fall 2006 © UCBCS 152 L4: Testing and TeamworkClimbing the Hierarchy: Multi-unit Testingcomplete processor testingHow to choose partition?unit testingHow to create specification?Top-downtestingBottom-uptestingRemove connected blocksfrom design.Test in isolation againstspecification.multi-unit testinghow it worksUC Regents Fall 2006 © UCBCS 152 L4: Testing and TeamworkTop-downtestingBottom-uptestingProcessor Testing with Self-Checking Unitscomplete processor testingunit testingmulti-unit testinghow it worksAdd self-checking to unitsPerform complete processor testingprocessortestingwithself-checksGood for Xilinx? ModelSim?Why not use self-checks for all tests?UC Regents Fall 2006 © UCBCS 152 L4: Testing and TeamworkTesting: Verification vs. Diagnosticscomplete processor testingTop-downtestingBottom-uptestingunit testingmulti-unit testingprocessortestingwithself-checksWhich testing types are good for verification? For diagnostics?Verification:A yes/no answer to the question “Does the processor have one more bug?”Diagnostics:Clues to help find and fix the bug.UC Regents Fall 2006 © UCBCS 152 L4: Testing and TeamworkXilinx: Observability and Controllabilitycomplete processor testingTop-downtestingBottom-uptestingunit testingmulti-unit testingprocessortestingwithself-checksFor early labs, use ChipScope for observability.Observability:Can I sense the state I need to diagnose a bug on the board?Controllability:Can I force a flip-flop into known state to diagnose bugs on the board?For later labs ...UC Regents Fall 2006 © UCBCS 152 L4: Testing and Teamwork... use switches and LEDs on the board.SwitchesLEDSLEDSCS 152 L4: Testing and Teamwork UC Regents Fall 2006 © UCBWriting a Test PlanUC Regents Fall 2006 © UCBCS 152 L4: Testing and TeamworkThe testing timeline ...complete processor testingTop-downtestingBottom-uptestingunit testingmulti-unit testingprocessortestingwithself-checksprocessorassemblycompletecorrectlyexecutes singleinstructionscorrectlyexecutes shortprogramsTimeEpoch 1 Epoch 2 Epoch 3 Epoch 4Plan in advance what tests to do when ...UC Regents Fall 2006 © UCBCS 152 L4: Testing and TeamworkAn example test plan ...processorassemblycompletecorrectlyexecutes singleinstructionscorrectlyexecutes shortprogramsTimeEpoch 1 Epoch 2 Epoch 3 Epoch 4unit testingearlymultiunit testinglaterprocessortestingwithself-checksmulti-unit testingunit testingdiagnosticscomplete processor testingverificationprocessortestingwithself-checksdiagnosticsprocessortestingwithself-checksmulti-unit testingunit testingdiagnosticscomplete processor testingTop-downtestingBottom-uptestingunit testingmulti-unit testingprocessortestingwithself-checksUC Regents Fall 2006 © UCBCS 152 L4: Testing and TeamworkSpr 05: “Works in Modelsim, not on board”In the end, Team Ergo failed because they didn't figure out how to handle some write buffer conditions. They passed most tests but not that one.As far as checkoffs go, Ergo passed the following in simulation: basic, corner, hammer, 3/8 tests for base, extra. Nothing worked on board.Ted Hong, TA Spring 05.UC Regents Fall 2006 © UCBCS 152 L4: Testing and TeamworkSolution: get confidence in “going to board” earlier ...processorassemblycompletecorrectlyexecutes singleinstructionscorrectlyexecutes shortprogramsTimeEpoch 1 Epoch 2 Epoch 3 Epoch 4complete processor testingTop-downtestingBottom-uptestingunit testingmulti-unit testingprocessortestingwithself-checksModelSim20 %Xilinx80 %ModelSim80 %Xilinx20 %ModelSim20 %Xilinx80 %ModelSim20 %Xilinx80 %Catch “warnings and errors”, signal name misspellings.Solving “Works in ModelSim, not on board”Errors: “latch generated”, “combinational loop detected”, etcCS 152 L4: Testing and Teamwork UC Regents Fall 2006 © UCBUnit TestingUC Regents Fall 2006 © UCBCS 152 L4: Testing and
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