CS 152 L09 Performance () UC Regents Fall 2004 © UCB2004-09-28 Dave Patterson(www.cs.berkeley.edu/~patterson)John Lazzaro (www.cs.berkeley.edu/~lazzaro)www-inst.eecs.berkeley.edu/~cs152/CS152 – Computer Architecture andEngineeringLecture 9 – Performance1CS 152 L09 Performance () UC Regents Fall 2004 © UCBLast Time: Microcode, Multi-Cycle 5CS 152 L09 Multicycle (25) Fall 2004 © UC RegentsController Design• The state diagrams that arise define the controller for an instruction set processor are highly structured• Use this structure to construct a simple “microsequencer” • Control reduces to programming this very simple devicemicroprogrammingop-codeMap ROMMicro-PCZ I Ldatapath controltakenCS 152 L09 Multicycle (26) Fall 2004 © UC RegentsOur Microsequencerop-codeMap ROMMicro-PCZ I Ldatapath controltakenCS 152 L09 Multicycle (27) Fall 2004 © UC RegentsAdding the Dispatch ROM•Sequencer-based control– Called “microPC” or “µPC” vs. state registerControl Value Effect00 Next µaddress = 001 Next µaddress = dispatch ROM 10 Next µaddress = µaddress + 1ROM:OpcodemicroPC1µAddressSelectLogicAdderROMMux0012R-type 000000 0100BEQ 000100 0011ori 001101 0110LW 100011 1000SW 101011 1011CS 152 L09 Multicycle (28) Fall 2004 © UC Regentssequencercontrolmicro-PCµ-sequencer:fetch,dispatch,sequentialDispatchROMOpcodeInputsMicroprogrammingµ-Code ROMTo DataPathDecodeDecodedatapath controlmicroinstruction (µ)CS 152 L09 Multicycle (29) Fall 2004 © UC RegentsMicroprogramming• Microprogramming is a convenient method for implementing structured control state diagrams:– Random logic replaced by microPC sequencer and ROM– Each line of ROM called a microinstruction: contains sequencer control + values for control points– To reduce confusion, normal instruction (e.g., MIPS addu) called “macroinstruction”– limited state transitions: branch to zero, next sequential,branch to µinstruction address from dispatch ROM• Control design reduces to Microprogramming– Part of the design process is to develop a “language” that describes control and is easy for humans to understandCS 152 L09 Multicycle (30) Fall 2004 © UC Regents“Macroinstruction” InterpretationMainMemoryexecutionunitcontrolmemoryCPUADDSUBANDDATA...User program plus Datathis can change!AND microsequencee.g., FetchCalc Operand AddrFetch Operand(s)CalculateSave Answer(s)one of these ismapped into oneof these2CS 152 L09 Performance () UC Regents Fall 2004 © UCBToday’s Lecture - PerformanceMeasurement: what, why, howThe performance equationHow energy limits performanceAmdahl’s law3UC Regents Fall 2004 © UCBCS 152 L09 Performance ()Performance Measurement(as seen by the customer)4CS 152 L09 Performance () UC Regents Fall 2004 © UCBWho (sensibly) upgrades CPUs often?A professional who turns CPU cycles into money, and who is cycle-limited.Artist tool: animation, video special effects.5CS 152 L09 Performance () UC Regents Fall 2004 © UCBHow to decide to buy a new machine?Measure After Effects “execution time” on a representative render “workload” “Night flight”City map and cloudscomputed“on the fly” with fractalsCPU intensive Trivial I/O6CS 152 L09 Performance () UC Regents Fall 2004 © UCB Interpreting Execution TimePerformance1Execution Time== 2.85 renders/hour1.5 GHz PB (Y) is N times faster than 1.25 GHz PB (X). N is ?N =Performance (Y)Execution Time (Y)Execution Time (X)Performance (X)== 1. 19PB 1.5 Ghz : 3. 4 renders/hour. PB 1.25 : 2.85 renders/hour.Does artist productivity really increase?Execution Time: 1265 secondsPowerBookG41.25 GHz7CS 152 L09 Performance () UC Regents Fall 2004 © UCBExecution Time: Time for 1 job to complete 2 CPUs: Execution Time vs ThroughputThroughput: # jobs/hour completed (not serialized)Could G5 and Opteron have similar Throughput? Why?Assume G5 MP executiontime faster because AE doesnot use both Opteron CPUs.1.8xfaster.What does this imply?2 CPUs vs1 CPU,otherwisesimilar8UC Regents Fall 2004 © UCBCS 152 L09 Performance ()Performance Measurement(as seen by a CPU designer)Q. Why do we care about After Effect’s performance?A. We want the CPU we are designing to run it well !9CS 152 L09 Performance () UC Regents Fall 2004 © UCBStep 1: Analyze the right measurement!CPU Time:Time the CPU spends running program under measurement.Response Time:Total time: CPU Time + time spent waiting (for disk, I/O, ...).Guides CPU designGuides system designHow to measure CPU time?% time <program name>25.77u 0.72s 0:29.17 90.8% How do designersuse these two numbers?10CS 152 L09 Performance () UC Regents Fall 2004 © UCBAdministrivia - Adjust Class Time ?We have permission to stay in thisroom past 12:30.A: Lecture from 11:10 to 12:30B: Lecture from 11:15 to 12:35C: Lecture from 11:20 to 12:40Does anyone have a class that starts 12:40?Class time options (all “sharp” time)11CS 152 L09 Performance () UC Regents Fall 2004 © UCBAdministrivia - Mid-Term is Coming!Mid-term review session: Sunday 10/10, 7-9 PM, 306 Soda.Mid-term: Tuesday 10/12, 5:30-8:30 PM, 101 Morgan. No class on Tuesday.After exam: Pizza at LaVal’s, on us!12CS 152 L09 Performance () UC Regents Fall 2004 © UCBAdministrivia - This Week’s DeadlinesHomework 2 due 9/29 (tomorrow)!283 Soda, in CS 152 box at 5 PMLab 2 Xilinx demo on Friday 10/1Lab 2 due Monday 10/4, 11:59 PMOn Tuesday 10/5, onto the Pipelining Lab!13CS 152 L09 Performance () UC Regents Fall 2004 © UCB CPU time: Proportional to Instruction CountCPU timeProgramMachine InstructionsProgramQ. Static count?(lines of program printout)Or dynamic count? (trace of execution)Rationale: Every additional instruction you execute takes time.Q. What type of computer architect influences the number of instructions a given program needs?A. Instruction set architect.A. Dynamic.Q. Once ISA is set, who can influence instructioncount?A. Compiler writer,application developer.14CS 152 L09 Performance () UC Regents Fall 2004 © UCB CPU time: Proportional to Clock PeriodQ. What ultimately limitsan architect’s ability to reduce clock period ?TimeProgramTimeOne Clock PeriodA. Clock-to-Q, setup times.Q. How can architects (not technologists) reduce clock period?A. Shorten the machine critical path.Rationale: We measure each instruction’sexecution time in “number of cycles”. By shortening the period for each cycle, we shorten execution time.15CS 152 L09 Performance () UC Regents Fall 2004 © UCB Completing the
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