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Berkeley COMPSCI 152 - ISAs, Microprogramming and Pipelining

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Problem 1: CISC, RISC, and Stack: Comparing ISAsProblem 2: Microprogramming and Bus-Based ArchitecturesCS152 Computer Architecture andEngineeringISAs, Microprogramming and PipeliningJanuary 25, 2010Assigned January26Problem Set #1Due February 11http://inst.eecs.berkeley.edu/~cs152/sp10The problem sets are intended to help you learn the material, and we encourage you tocollaborate with other students and to ask questions in discussion sections and office hours tounderstand the problems. However, each student must turn in his own solution to the problems.The problem sets also provide essential background material for the quizzes. The problem setswill be graded primarily on an effort basis, but if you do not work through the problem sets youare unlikely to succeed at the quizzes! We will distribute solutions to the problem sets on the daythe problem sets are due to give you feedback. Homework assignments are due at the beginningof class on the due date. Late homework will not be accepted.Problem 1: CISC, RISC, and Stack: Comparing ISAsIn this problem, your task is to compare three different ISAs. x86 is an extended accumulator,CISC architecture with variable-length instructions. MIPS64 is a load-store, RISC architecturewith fixed-length instructions. We will also look at a simple stack-based ISA.Problem 1.A CISCLet us begin by considering the following C code:int b; //a global variablevoid multiplyByB(int a){ int i, result; for(i = 0; i<b; i++){ result=result+a; }}Using gcc and objdump on a Pentium III, we see that the above loop compiles to the followingx86 instruction sequence. (On entry to this code, register %ecx contains i, and register %edxcontains result, and register %eax contains a. b is stored in memory at location 0x8049580)xor %edx,%edxxor %ecx,%ecx loop: cmp 0x8049580,%ecx jl L1 jmp done L1: add %eax,%edx inc %ecx jmp loop done: ...The meanings and instruction lengths of the instructions used above are given in the followingtable. Registers are denoted with RSUBSCRIPT, register contents with <RSUBSCRIPT>. Notice that the jump instruction jl (jump if less than) depends on SF and OF, which are statusflags. Status flags, also known as condition codes, are analogous to the condition register used inthe MIPS architecture. Status flags are set by the instruction preceding the jump, based on theresult of the computation. Some instructions, like the cmp instruction, perform a computation andInstruction Operation Lengthadd RDEST, RSRCRSRC  <RSRC> + <RDST>2 bytescmp imm32, RSRC2 Temp  <RSRC2> - MEM[imm32]6 bytesinc RDESTRDEST  <RDEST> + 11 bytejmp labeljump to the address specified by label 2 bytesjl labelif (SFOF) jump to the address specified by label2 bytesxor RDEST, RSRC RDEST  RDEST  RSRC2 bytesset status flags, but do not return any result. The meanings of the status flags are given in thefollowing table:Howmanybytesis the program? For the above x86 assembly code, how many bytes of instructions need to befetched if b = 10? Assuming 32-bit data values, how many bytes of data memory need to befetched? Stored?Problem 1.B RISCTranslate each of the x86 instructions in the following table into one or more MIPS64instructions. Place the L1 and loop labels where appropriate. You should use the minimumnumber of instructions needed to translate each x86 instruction. Assume that upon entry, R1contains b, R2 contains a, R3 contains i. R4 should receive result. If needed, use R5 as acondition register, and R6, R7, etc., for temporaries. You should not need to use any floating-point registers or instructions in your code. A description of the MIPS64 instruction setarchitecture can be found in Appendix B of Hennessy & Patterson. Name Purpose Condition ReportedOF Overflow Result exceeds positive or negative limit of number rangeSF Sign Result is negative (less than zero)x86 instruction label MIPS64 instruction sequencexor %edx,%edx xor %ecx,%ecx cmp 0x8049580,%ecxjl L1 jmp doneadd %eax,%edxinc %ecxjmp loop...done: ...How many bytes is the MIPS64 program using your direct translation? How many bytes ofMIPS64 instructions need to be fetched for b = 10 using your direct translation? Assuming 32-bitdata values, how many bytes of data memory need to be fetched? Stored?Problem 1.C StackIn a stack architecture, all operations occur on top of the stack. Only push and pop accessmemory, and all other instructions remove their operands from the stack and replace them withthe result. The hardware implementation we will assume for this problem set uses stack registersfor the top two entries; accesses that involve other stack positions (e.g., pushing or poppingsomething when the stack has more than two entries) use an extra memory reference. The tablebelow gives a subset of a simple stack-style instruction set. Assume each opcode is a single byte.Labels, constants, and addresses require two bytes.Translate the multiplyByB loop to the stack ISA. For uniformity, please use the same controlflow as in parts a and b. Assume that when we reach the loop, a is the only thing on the stack.Assume b is still at address 0x8000 (to fit within a 2 byte address specifier).How many bytes is your program? Using your stack translations from part (c), how many bytesof stack instructions need to be fetched for b = 10? Assuming 32-bit data values, how many bytesof data memory need to be fetched? Stored? If you could push and pop to/from a four-entryregister file rather than memory (the Java virtual machine does this), what would be the resultingnumber of bytes fetched and stored?Example instruction MeaningPUSH A push M[A] onto stackPOP A pop stack and place popped value in M[A]ADD pop two values from the stack; ADD them; push result onto stackSUB pop two values from the stack; SUBtract top value from the 2nd;push result onto stackZERO zeroes out the value at top of stackINC pop value from top of stack; increments value by onepush new value back on the stack BEQZ label pop value from stack; if it’s zero, continue at label;else, continue with next instructionBNEZ label pop value from stack; if it’s not zero, continue at label;else, continue with next instructionGOTO label continue execution at location labelProblem 1.D ConclusionsIn just a few sentences, compare the three ISAs you have studied with respect to


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