CS 152 Computer Architecture and Engineering Introduction to Architectures for Digital Signal Processing Nov 12 1997 Bob Brodersen http infopad eecs berkeley edu 1 Processor Applications Pentiums Alpha s SPARC Used for general purpose software Heavy weight OS UNIX NT Workstations PC s Embedded processors and processor cores ARM 486SX Hitachi SH7000 NEC V800 Single program Lightweight often realtime OS DSP support Cellular phones consumer electronics e g CD players Microcontrollers Extremely cost sensitive Small word size 8 bit common Highest volume processors by far Automobiles toasters thermostats Increasing volume Increasing Cost General Purpose high performance 2 Performance The Processor Design Space Application specific architectures for performance Embedded processors Microprocessors Performance is everything Software rules Microcontrollers Cost is everything Cost 3 World s Cellular Subscribers Millions 700 Will provide a ubiquitous infrastructure for wireless data as well as voice 600 500 400 300 Digital 200 100 0 1993 Analog 1994 1995 1996 1997 1998 1999 2000 2001 Year Source Ericsson Radio Systems Inc Multimedia I O Architecture Radio Modem Embedded Processor Sched ECC Pact Interface Low Power Bus FB Data Flow Fifo Fifo Video Decomp Pen SRAM Graphics Audio Video 5 Embedded applications E g Multimedia terminal electronics Graphics Out Uplink Radio Video I O Downlink Radio Voice I O Pen In P Video Unit Coms Future chips will be a mix of processors memory and dedicated hardware for specific algorithms and I O Memory custom DSP 6 Requirements of the Embedded Processors Optimized for a single program code often in on chip ROM or off chip EPROM Minimum code size one of the motivations initially for Java Performance obtained by optimizing datapath Low cost Lowest possible area Technology behind the leading edge High level of integration of peripherals reduces system cost Fast time to market Compatible architectures e g ARM allows reuseable code Customizable core Low power if application requires portability 7 Area of processor cores Cost Nintendo processor Cellular phones 8 Another figure of merit Computation per unit area Nintendo processor Cellular phones 9 National Semiconductor Embedded Processor Family Simple architecture 3 stage pipeline fetch decode execute Minimum power and size Short pipeline avoids branch prediction and bypass Versions range from 8 64 bit choose minimum that meets requirements 10 Code size If a majority of the chip is the program stored in ROM then code size is a critical issue The Piranha has 3 sized instructions basic 2 byte and 2 byte plus 16 or 32 bit immediate 11 Example application single chip system 12 The DSP Module DSPM Vector instructions directly supported Pipelined datapath supprts single cycle Multiply Add Shift Load Store and Pointer adjustment Operates in parallel to processor core Saturation overflow and rounding for ALU operations Automatic support for cyclic buffers modulo arithmetic 13 The National DSP Module Architecture Zero overhead repeat Three simultaneous addresses X Y Z Single cycle MAC support is typical for DSP acceleration 14 The 486 Embedded Processor 15 The Embedded Features of the 486 GX Said to be designed for embedded batteryoperated and hand held applications Fully static design clock can stop and all state is kept Auto Clock Freeze stops circuits which are not being used in a given instruction gated clocks Stop Clock 60 W Stop Grant clock runs but no program execution 40 85 mW Split power supply 2 0 3 3 Volt core 3 3V I O 16 Power C V2 fclock Power 130 mW 350 mW 190 mW 430 mW 290 mW 540 mW 490 mW 730 mW 17 mW 20 mW 23 mW 30 mW Note the clock rates 17 Characterizing programs for their energy consumption Process Subframe 330 W ComputeLag 107 W IFilterCodebook 63 W QuantizeGains 46 W CodebookSearch 44 W UpdateFilterState 8 W OrthogonalizeCodebook 6 W ComputeWeightedInput ComputeLag R dotprod res res for lag 0 127 lp getLT lt G dotprod lp lp 22 W ThetaToCodeword 8 W Top four functions account for 90 of the power 65 of power dissipation in dot vector products data obtained from profiling of C code weighted with estimated instruction energy costs 18 An architecture optimized for multiplyaccumulate AddressGen Memory MAC L G AddressGen Memory MAC C Control Processor Energy Flexibility Tradeoff s Arm 6 core 5V 20 MHz 02 MIPS mW ZSP DSP Superscaler 3V 200 MHz 3 MOPS mW Reconfigurable Dot Vector Processor 1 5V 30 MHz 5 9 MIPS mW MOPS millions of operations sec millions of MACS sec 19
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