Review recall General C L Cell Delay Model CS152 Computer Architecture and Engineering Lecture 5 B Combinational Logic Cell X Delay Va Vout Vout A X Cout X X X X The Design Process X delay per unit load Internal Delay Ccritical Cout Combinational Cell symbol is fully specified by February 10 2003 functional input output behavior truth table logic equation VHDL load factor of each input critical propagation delay from each input to each output for each transition THL A o Fixed Internal Delay Load dependent delay x load John Kubiatowicz www cs berkeley edu kubitron lecture slides http www inst eecs berkeley edu cs152 2 10 03 CS152 Kubiatowicz Lec4 1 UCB Spring 2003 Review Storage Element s Timing Model Q Clk Setup D Hold Don t Care Don t Care Clock to Q Q CS152 Kubiatowicz Lec4 2 UCB Spring 2003 Review Critical Path Cycle Time Clk D Linear model composes 2 10 03 Unknown Setup Time Input must be stable BEFORE trigger clock edge Hold Time Input must REMAIN stable after trigger clock edge Clock to Q time Output cannot change instantaneously at the trigger clock edge Similar to delay in logic gates two components Internal Clock to Q Load dependent Clock to Q Critical path the slowest path between any two storage devices Cycle time is a function of the critical path must be greater than Clock to Q Longest Path through Combination Logic Setup Typical for class 1ns Setup 0 5ns Hold 2 10 03 UCB Spring 2003 CS152 Kubiatowicz Lec4 3 2 10 03 UCB Spring 2003 CS152 Kubiatowicz Lec4 4 Review Tricks to Reduce Cycle Time Review Karnaugh Map for easier simplification Reduce the number of gate levels A S1 S0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 B A B C C D D Use esoteric dynamic timing methods Pay attention to loading One gate driving many gates is a bad idea C 0 1 0 1 0 1 0 1 S1 S0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 0 s0 CS152 Kubiatowicz Lec4 5 UCB Spring 2003 Review DeMorgan s theorem Push Bubbles and Morph A Out 0 0 1 1 B B Out 0 1 0 1 A 1 1 1 0 A B Out A B 0 0 0 1 1 0 1 1 0 0 1 1 Out B 00 01 11 10 0 0 0 1 1 1 0 1 0 1 6 6 6 6 6 6 2 10 03 CS152 Kubiatowicz Lec4 6 UCB Spring 2003 Review Integrated Circuit Costs Die cost B Out 0 1 0 1 1 0 0 0 Wafer cost Dies per Wafer Die yield Dies per wafer S Wafer diam 2 2 S Wafer diam Test dies Wafer Area Die Area 2 Die Area Die Area Out A B A B Out A B A B A 1 NOR Gate NAND Gate A 0 0 Next State INV4x 2 10 03 1 0 s1 Comb Logic State 2 flops Clarge 1 1 C INV4x 0 1 6 6 6 Avoid using a small gate to drive a long wire Use multiple stages to drive large load 00 01 11 10 0 A 1 1 0 0 B Out 1 0 1 0 1 1 1 0 A B Out A B 0 0 0 1 1 0 1 1 A 1 1 0 0 B Out 1 0 1 0 1 0 0 0 Die Yield Wafer yield 1 Defects per unit area Die Area D D Die Cost is goes roughly with die area 3 or die area 4 2 10 03 UCB Spring 2003 CS152 Kubiatowicz Lec4 7 2 10 03 UCB Spring 2003 CS152 Kubiatowicz Lec4 8 Design Process cont The Design Process To Design Is To Represent Design Finishes As Assembly Design activity yields description representation of an object Design understood in terms of components and how they have been assembled Traditional craftsman does not distinguish between the conceptualization and the artifact Separation comes about because of complexity CPU Datapath ALU Top Down decomposition of complex functions behaviors into more primitive functions The concept is captured in one or more representation languages This process IS design Regs Control Shifter Nand Gate bottom up composition of primitive building blocks into more complex assemblies Design Begins With Requirements Design is a creative process not a simple method Functional Capabilities what it will do Performance Characteristics Speed Power Area Cost 2 10 03 UCB Spring 2003 CS152 Kubiatowicz Lec4 9 Design Refinement 2 10 03 CS152 Kubiatowicz Lec4 10 UCB Spring 2003 Design as Search Informal System Requirement Problem A Initial Specification Strategy 1 Strategy 2 Intermediate Specification SubProb 1 refinement increasing level of detail Final Architectural Description BB1 BB2 SubProb2 SubProb3 BB3 BBn Design involves educated guesses and verification Intermediate Specification of Implementation Given the goals how should these be prioritized Given alternative design pieces which should be selected Given design space of components assemblies which part will yield the best solution Final Internal Specification Physical Implementation 2 10 03 UCB Spring 2003 CS152 Kubiatowicz Lec4 11 Feasible good choices vs Optimal choices 2 10 03 UCB Spring 2003 CS152 Kubiatowicz Lec4 12 Problem Design a fast ALU for the MIPS ISA Requirements MIPS ALU requirements Add AddU Sub SubU AddI AddIU Must support the Arithmetic Logic operations Tradeoffs of cost and speed based on frequency of occurrence hardware budget 2 s complement adder sub with overflow detection And Or AndI OrI Xor Xori Nor Logical AND logical OR XOR nor SLTI SLTIU set less than 2 s complement adder with inverter check sign bit of result ALU from from CS 150 P H book chapter 4 supports these ops 2 10 03 CS152 Kubiatowicz Lec4 13 UCB Spring 2003 MIPS arithmetic instruction format 31 R type I Type 25 20 op Rs Rt op Rs Rt 15 5 Rd 0 Trick 1 Break the problem into simpler problems solve them and glue together the solution Immed 16 op funct Type op funct ADDI 10 xx ADD 00 40 Type ADDIU 11 xx ADDU 00 41 SLTI 12 xx SUB 00 42 SLT SLTIU 13 xx SUBU 00 43 CS152 Kubiatowicz Lec4 14 UCB Spring 2003 Design Trick divide conquer funct Type 2 10 03 Example assume the immediates have been taken care of before the ALU op funct 00 add 00 50 01 addU 00 51 02 sub 00 52 03 subU SLTU 00 53 04 and or 10 operations 4 bits ANDI 14 xx AND 00 44 05 ORI 15 xx OR 00 45 06 xor XORI 16 xx XOR 00 46 07 nor LUI 17 xx NOR 00 47 12 slt 13 sltU Signed arithmetic generate overflow no carry 2 10 03 UCB Spring 2003 CS152 Kubiatowicz Lec4 15 2 10 03 UCB Spring 2003 CS152 Kubiatowicz Lec4 16 Refined Requirements Behavioral Representation verilog 1 Functional Specification inputs 2 x 32 bit operands A B 4 bit mode outputs 32 bit result S 1 bit carry 1 bit overflow operations add addu sub subu and or …
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