2/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec4.1February 10, 2003John Kubiatowicz (www.cs.berkeley.edu/~kubitron)lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/CS152Computer Architecture and EngineeringLecture 5The Design Process2/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec4.2Review: recall General C/L Cell Delay Model° Combinational Cell (symbol) is fully specified by:• functional (input -> output) behavior- truth-table, logic equation, VHDL• load factor of each input• critical propagation delay from each input to each output for each transition- THL(A, o) = Fixed Internal Delay + Load-dependent-delay x load ° Linear model composesCoutVoutABX...CombinationalLogic CellCoutDelayVa -> VoutXXXXXXCcriticalInternal Delaydelay per unit load2/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec4.3Review: Storage Element’s Timing Model° Setup Time: Input must be stable BEFORE trigger clock edge° Hold Time: Input must REMAIN stable after trigger clock edge° Clock-to-Q time:• Output cannot change instantaneously at the trigger clock edge• Similar to delay in logic gates, two components:- Internal Clock-to-Q- Load dependent Clock-to-Q° Typical for class: 1ns Setup, 0.5ns HoldDQD Don’t CareDon’t CareClkUnknownQSetupHoldClock-to-Q2/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec4.4Review: Critical Path & Cycle Time° Critical path: the slowest path between any two storage devices° Cycle time is a function of the critical path° must be greater than:Clock-to-Q + Longest Path through Combination Logic + SetupClk............2/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec4.5Review: Tricks to Reduce Cycle Time° Reduce the number of gate levels° Use esoteric/dynamic timing methods° Pay attention to loading° One gate driving many gates is a bad idea° Avoid using a small gate to drive a long wire° Use multiple stages to drive large loadABCDABCDINV4xINV4xClarge2/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec4.6Review: Karnaugh Map for easier simplificationS1S0CS1’S0’000 00001 01010 01011 10100 10101 11110 11111 0000 01 11 100001110101s1()()()66&6&666 ⋅+⋅+⋅⋅=′State2 flopsCombLogicNext StateC00 01 11 100011011001s0()()&6&66⋅+⋅=′2/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec4.7Review: DeMorgan’s theorem: Push Bubbles and Morph NAND GateNOR GateOutABABOutABOut11100011011 0ABOutOutABOut = A • B = A + BOut = A + B = A • BABOut00 101 010 011 0ABOut11 110 101 100 000011011ABABOut11 110 001 000 000011011AB2/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec4.8Defects_per_unit_area * Die_AreaDD}Review: Integrated Circuit CostsDie Cost is goes roughly with (die area)3or (die area)4{ 1+Die cost = Wafer costDies per Wafer * Die yieldDies per wafer = S * ( Wafer_diam / 2)2– S * Wafer_diam – Test dies | Wafer AreaDie Area 2 * Die Area Die AreaDie Yield = Wafer yield2/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec4.9The Design Process"To Design Is To Represent"Design activity yields description/representation of an object-- Traditional craftsman does not distinguish between the conceptualization and the artifact-- Separation comes about because of complexity-- The concept is captured in one or more representation languages-- This process IS designDesign Begins With Requirements-- Functional Capabilities: what it will do-- Performance Characteristics: Speed, Power, Area, Cost, . . .2/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec4.10Design Process (cont.)Design Finishes As Assembly-- Design understood in terms ofcomponents and how they havebeen assembled-- Top Down decomposition ofcomplex functions (behaviors)into more primitive functions-- bottom-up composition of primitivebuilding blocks into more complex assembliesCPUDatapath ControlALU Regs ShifterNandGateDesign is a "creative process," not a simple method2/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec4.11Design RefinementInformal System RequirementInitial SpecificationIntermediate SpecificationFinal Architectural DescriptionIntermediate Specification of ImplementationFinal Internal SpecificationPhysical Implementationrefinementincreasing level of detail2/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec4.12Design as Search Design involves educated guesses and verification-- Given the goals, how should these be prioritized?-- Given alternative design pieces, which should be selected?-- Given design space of components & assemblies, which part will yieldthe best solution?Feasible (good) choices vs. Optimal choicesProblem AStrategy 1 Strategy 2SubProb 1SubProb2SubProb3BB1 BB2 BB3 BBn2/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec4.13Problem: Design a “fast” ALU for the MIPS ISA° Requirements?° Must support the Arithmetic / Logic operations° Tradeoffs of cost and speed based on frequency of occurrence, hardware budget2/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec4.14MIPS ALU requirements° Add, AddU, Sub, SubU, AddI, AddIU • => 2’s complement adder/sub with overflow detection° And, Or, AndI, OrI, Xor, Xori, Nor• => Logical AND, logical OR, XOR, nor° SLTI, SLTIU (set less than)• => 2’s complement adder with inverter, check sign bit of result° ALU from from CS 150 / P&H book chapter 4 supports these ops2/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec4.15MIPS arithmetic instruction format° Signed arithmetic generate overflow, no carryR-type:I-Type:31 25 20 15 5 0op Rs Rt Rd functop Rs Rt Immed 16Type op functADDI 10 xxADDIU 11 xxSLTI 12 xxSLTIU 13 xxANDI 14 xxORI 15 xxXORI 16 xxLUI 17 xxType op functADD 00 40ADDU 00 41SUB 00 42SUBU 00 43AND 00 44OR 00 45XOR 00 46NOR 00 47Type op funct00 5000 51SLT 00 52SLTU 00 532/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec4.16Design Trick: divide & conquer° Trick #1: Break the problem into simpler problems, solve them and glue together the solution° Example: assume the immediates have been taken care of before the ALU• 10 operations (4 bits)00 add01 addU02 sub03 subU04 and05 or06 xor07 nor12 slt13 sltU2/10/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec4.17Refined Requirements(1) Functional Specificationinputs: 2 x 32-bit operands A, B, 4-bit modeoutputs: 32-bit result S, 1-bit carry, 1 bit overflowoperations: add, addu, sub, subu, and, or, xor, nor, slt, sltU(2) Block Diagram (schematic symbol, Verilog description)ALUALUABmovfS32 32324c2/10/03 ©UCB Spring 2003CS152 /
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