CS 152 L3: Single Cycle Wrap-up UC Regents Fall 2006 © UCB2006-9-5John Lazzaro (www.cs.berkeley.edu/~lazzaro)CS 152 Computer Architecture and EngineeringLecture 3 – Single Cycle Wrap-Up + VLIWwww-inst.eecs.berkeley.edu/~cs152/TAs: Udam Saini and Jue SunUC Regents Fall 2006 © UCBCS 152 L3: Single Cycle Wrap-upLast Time: Goal #1, an R-format CPUopcode rs rt rd functshamtSyntax: ADD $8 $9 $10 Semantics: $8 = $9 + $10Sample program:ADD $8 $9 $10SUB $4 $8 $3AND $9 $8 $4...How registers get their initial values are not of concern to us right now.No loads or stores: machine has no use for data memory, only instruction memory.No branches or jumps: machine only runs straight line code.UC Regents Fall 2006 © UCBCS 152 L3: Single Cycle Wrap-up Last Time: An R-format CPU design32rd1RegFile32rd2WE32wd5rs15rs25ws32ALU3232opopcode rs rt rd functshamtDecode fields to get : ADD $8 $9 $10 LogicUC Regents Fall 2006 © UCBCS 152 L3: Single Cycle Wrap-upLast Time: Goal #2, I-format instructionsSyntax: ORI $8 $9 64 Semantics: $8 = $9 | 6416-bit immediate extended to 32 bits.In this example, $9 is rs and $8 is rt. Zero-extend: 0x8000 ⇨0x00008000Sign-extend: 0x8000 ⇨0xFFFF8000Some MIPS instructions zero-extend immediate field, other instructions sign-extend.CS 152 L06 Single Cycle 1 (6) UC Regents Fall 2004 © UCBStep 1a: The MIPS-lite Subset for today° ADD and SUB• addU rd, rs, rt• subU rd, rs, rt° OR Immediate:• ori rt, rs, imm16° LOAD and STORE Word• lw rt, rs, imm16• sw rt, rs, imm16° BRANCH:• beq rs, rt, imm16op rs rt rd shamt f unct0611162126316 bits 6 bits5 bits5 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsUC Regents Fall 2006 © UCBCS 152 L3: Single Cycle Wrap-up Last Time: The merged data path ...32rd1RegFile32rd2WE32wd5rs15rs25ws32ALU3232opopcode rs rt rd functshamtCS 152 L06 Single Cycle 1 (6) UC Regents Fall 2004 © UCBStep 1a: The MIPS-lite Subset for today° ADD and SUB• addU rd, rs, rt• subU rd, rs, rt° OR Immediate:• ori rt, rs, imm16° LOAD and STORE Word• lw rt, rs, imm16• sw rt, rs, imm16° BRANCH:• beq rs, rt, imm16op rs rt rd shamt f unct0611162126316 bits 6 bits5 bits5 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsRegDestALUsrcExtExtOpALUctrUC Regents Fall 2006 © UCBCS 152 L3: Single Cycle Wrap-upToday’s Lecture: Single-Cycle Wrap-upDesign stand-alone machines for other major classes of instructions:branches, load/store.Implementing control structures for the single-cycle datapath.And also, Design Notebook for Lab 2 ...Very Long Instruction Words (VLIW): Doing more work in a single cycle.CS 152 L3: Single Cycle Wrap-up UC Regents Fall 2006 © UCBMemory InstructionsUC Regents Fall 2006 © UCBCS 152 L3: Single Cycle Wrap-up Loads, Stores, and Data Memory ...32DoutData MemoryWE32Din32AddrSyntax: LW $1, 32($2) Syntax: SW $3, 12($4) Action: $1 = M[$2 + 32] Action: M[$4 + 12] = $3CS 152 L06 Single Cycle 1 (6) UC Regents Fall 2004 © UCBStep 1a: The MIPS-lite Subset for today° ADD and SUB• addU rd, rs, rt• subU rd, rs, rt° OR Immediate:• ori rt, rs, imm16° LOAD and STORE Word• lw rt, rs, imm16• sw rt, rs, imm16° BRANCH:• beq rs, rt, imm16op rs rt rd shamt f unct0611162126316 bits 6 bits5 bits5 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsZero-extend or sign-extend immediate field?Writes are clocked: If WE is high, memory Addr captures Din on positive edge of clock.Reads are combinational: Put a stable address on Addr,a short time later Dout is readyNote: Not a realistic main memory (DRAM) model ...CS 152 L3: Single Cycle Wrap-up UC Regents Fall 2006 © UCB Adding data memory to the data path32rd1RegFile32rd2WE32wd5rs15rs25wsCS 152 L06 Single Cycle 1 (6) UC Regents Fall 2004 © UCBStep 1a: The MIPS-lite Subset for today° ADD and SUB• addU rd, rs, rt• subU rd, rs, rt° OR Immediate:• ori rt, rs, imm16° LOAD and STORE Word• lw rt, rs, imm16• sw rt, rs, imm16° BRANCH:• beq rs, rt, imm16op rs rt rd shamt f unct0611162126316 bits 6 bits5 bits5 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsExtRegDestALUsrcExtOpALUctr32ALU3232opMemToReg32DoutData MemoryWE32DinAddrMemWrSyntax: LW $1, 32($2) Syntax: SW $3, 12($4) Action: $1 = M[$2 + 32] Action: M[$4 + 12] = $3RegWrLoad delay slot CPU, or not ?CS 152 L3: Single Cycle Wrap-up UC Regents Fall 2006 © UCBBranch InstructionsUC Regents Fall 2006 © UCBCS 152 L3: Single Cycle Wrap-up Conditional Branches in MIPS ...Syntax: BEQ $1, $2, 12Action: If ($1 != $2), PC = PC + 4CS 152 L06 Single Cycle 1 (6) UC Regents Fall 2004 © UCBStep 1a: The MIPS-lite Subset for today° ADD and SUB• addU rd, rs, rt• subU rd, rs, rt° OR Immediate:• ori rt, rs, imm16° LOAD and STORE Word• lw rt, rs, imm16• sw rt, rs, imm16° BRANCH:• beq rs, rt, imm16op rs rt rd shamt f unct0611162126316 bits 6 bits5 bits5 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsZero-extend or sign-extend immediate field?Action: If ($1 == $2), PC = PC + 4 + 48Immediate field codes # words, not # bytes.Why is this encoding a good idea?Why is this extension method a good idea?CS 152 L3: Single Cycle Wrap-up UC Regents Fall 2006 © UCB Adding branch testing to the data path32rd1RegFile32rd2WE32wd5rs15rs25wsCS 152 L06 Single Cycle 1 (6) UC Regents Fall 2004 © UCBStep 1a: The MIPS-lite Subset for today° ADD and SUB• addU rd, rs, rt• subU rd, rs, rt° OR Immediate:• ori rt, rs, imm16° LOAD and STORE Word• lw rt, rs, imm16• sw rt, rs, imm16° BRANCH:• beq rs, rt, imm16op rs rt rd shamt f unct0611162126316 bits 6 bits5 bits5 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsExtRegDestALUsrcExtOpALUctr32ALU3232opMemToReg32DoutData MemoryWE32DinAddrMemWrSyntax: BEQ $1, $2, 12Action: If ($1 != $2), PC = PC + 4Action: If
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