CS 152 Computer Architecture and Engineering Lecture 3 Single Cycle Wrap Up VLIW 2006 9 5 John Lazzaro www cs berkeley edu lazzaro TAs Udam Saini and Jue Sun www inst eecs berkeley edu cs152 CS 152 L3 Single Cycle Wrap up UC Regents Fall 2006 UCB Last Time Goal 1 an R format CPU Syntax ADD 8 9 10 opcode Sample ADD 8 SUB 4 AND 9 rs program 9 10 8 3 8 4 How registers get their initial values are not of concern to us right now CS 152 L3 Single Cycle Wrap up rt Semantics 8 9 10 rd shamt funct No branches or jumps machine only runs straight line code No loads or stores machine has no use for data memory only instruction memory UC Regents Fall 2006 UCB Last Time An R format CPU design Decode fields to get ADD 8 9 10 opcode rs rt rd shamt funct Logic op 5 5 5 32 RegFile rs1 rd1 rs2 32 ws 32 wd 32 CS 152 L3 Single Cycle Wrap up rd2 32 A L U 32 WE UC Regents Fall 2006 UCB op Time rs Goal rt rd shamt funct Last 2 I format instructions 6 bits 5 bits 5 bits Syntax ORI 8 9 64 31 26 op 6 bits 31 26 ord op In 6 bits 21 5 bits 5 bits 6 bits Semantics 8 9 64 16 rs rt 5 bits 5 bits 21 16 this example 9 rs rt 5 bits 5 bits 0 immediate 16 bits is rs and 8 is rt 0 immediate 16 bits 16 bit immediate extended to 32 bits 31 26 21 16 Zero extend 0x8000 0x00008000 0 op rs rt immediate 0x8000 0xFFFF8000 6 bitsSign extend 5 bits 5 bits 16 bits Some MIPS instructions zero extend immediate field other instructions sign extend CS 152 L3 Single Cycle Wrap up UC Regents Fall 2006 UCB Last Time The merged data path opcode rs rt rd shamt funct ALUctr op The MIPS lite Subset for today 5 31 5 5 26 op RegDest 6 bits 32 RegFile rs1 rd1 rs2 ws wd 21 rs 5 bits rd2 WE 32 32 32 16 rt 5 bits Ext ExtOp 31 26 op 6 bits 21 rs 5 bits CS 152 L3 Single Cycle Wrap up A L 6U 1132 rd 5 bits shamt 5 bits 0 funct 6 bits ALUsrc 16 rt 5 bits 32 0 immediate 16 bits UC Regents Fall 2006 UCB Today s Lecture Single Cycle Wrap up Design stand alone machines for other major classes of instructions branches load store Implementing control structures for the single cycle datapath Very Long Instruction Words VLIW Doing more work in a single cycle And also Design Notebook for Lab 2 CS 152 L3 Single Cycle Wrap up UC Regents Fall 2006 UCB Memory Instructions CS 152 L3 Single Cycle Wrap up UC Regents Fall 2006 UCB 6 bits 5 bits 5 bits 5 bits 5 bits Loads Stores and Data Memory 31 26 21 6 bits 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits Syntax LW 1 32 2 31 26 21 16 Syntax SW 3 12 4 0 ord op immediate Action 1 rsM 2 rt32 Action M 4 12 3 6 bits 5 bits 5 bits 16 bits Zero extend or sign extend immediate field 31 32 26Memory Data opAddr 6 bits 21 rs 32 Dout 5 bits Reads are combinational 16 0 address on Addr rt Put a stableimmediate a short time later Dout is ready 5 bits 16 bits Din 32 Writes are clocked If WE is high memory Addr captures Din on positive edge of clock Note Not a realistic main memory DRAM model WE CS 152 L3 Single Cycle Wrap up UC Regents Fall 2006 UCB Adding data memory to the data path 5 5 5 RegFile rs1 rd1 rs2 32 ws 32 ALUctr op 32 The MIPS lite Subset for today wd RegDest 31 32 rd2 Data Memory 32 A L U op 6 bits Addr 21 RegWr rs 5 bits 16 ALUsrc 11 rt rd 5 bits 5 bits Din 32 WE 6 ExtOp Load 31 delay26slot CPU 21or not 16 32 Dout WE Ext 26 32 shamt 5 bits 0 MemToReg MemWr funct 6 bits 0 op rs rt immediate 6 bitsLW 1 5 bits32 2 5 bits Syntax Syntax 16 SWbits 3 12 4 31 26 21 16 0 Word Action 1 M 2 32 Action M 4 12 3 op rs rt immediate CS 152 L3 Single Cycle Wrap up UC Regents Fall 2006 UCB Branch Instructions CS 152 L3 Single Cycle Wrap up UC Regents Fall 2006 UCB 6 bits 5 bits 5 bits 5 bits 5 bits Conditional Branches in MIPS 31 26 21 6 bits 16 0 op rs rt immediate 6 bits 5 bits 5 bits 16 bits Syntax BEQ 1 21 2 12 16 31 26 ord op rs 2 rt PC PC immediate Action If 1 4 6 bits 5 bits 5 bits 16 bits 0 Action If 1 2 PC PC 4 48 31 26 21 16 Immediate field codes words not bytes rs rt idea immediate Why isopthis encoding a good 6 bits 5 bits 5 bits 0 16 bits Zero extend or sign extend immediate field Why is this extension method a good idea CS 152 L3 Single Cycle Wrap up UC Regents Fall 2006 UCB Adding branch testing to the data path 5 5 5 RegFile rs1 rd1 rs2 32 ws 32 ALUctr op The MIPS lite Subset for today wd RegDest 31 32 Data Memory A L U 32 32 Addr 21 RegWr rs 5 bits 26 21 Ext 32 Dout WE 26 op 6 bits 31 rd2 32 Din 32 16 ExtOp rt 5 bits ALUsrc 11 rd 5 bits 6 WE shamt MemWr funct 5 bits 6 bits Equal wire into control 16 0 op rs rt immediate 6 bits BEQ5 bits 5 bits 16 bits Syntax 1 2 12 Action 31 26If 121 2 16 PC PC 4 Word Action If 1 2 PC PCimmediate 4 48 op rs rt CS 152 L3 Single Cycle Wrap up 0 MemToReg 0 UC Regents Fall 2006 UCB Recall Straight line Instruction Fetch Instr Mem 32 Data Fetching straight line MIPS instructions requires a machine that generates this timing diagram Addr 32 CLK Addr PC Data PC 4 IMem PC IMem PC 4 PC 8 IMem PC 8 PC Program Counter points to next instruction CS 152 L3 Single Cycle Wrap up UC Regents Fall 2006 UCB Recall Straight line Instruction Fetch Syntax BEQ 1 2 12 How do we add this behavior Action If 1 2 PC PC 4 Action If 1 2 PC PC 4 48 32 PC Instr Mem 32 32 32 D Q 32 Addr Data 32 0x4 Clk CLK Addr PC Data CS 152 L3 Single Cycle Wrap up PC 4 IMem PC IMem PC 4 PC 8 IMem PC 8 UC Regents Fall 2006 UCB Design Instruction Fetch with Branch Syntax BEQ 1 2 12 Action If 1 2 PC PC …
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