CS 152 Computer Architecture and Engineering Lecture 1 The MIPS ISA A An nd d aals lso aan o n iin n 2006 8 29 ttrro tto o o tth hee c co John Lazzaro ou urrsse www cs berkeley edu lazzaro e TAs Udam Saini and Jue Sun www inst eecs berkeley edu cs152 CS 152 L1 The MIPS ISA UC Regents Fall 2006 UCB CS 152 Computer Design Team Projects Single cycle CPU project 3 weeks Pipelined CPU 3 weeks Final Project 5 weeks IBM Power 5 die photo a die is an unpackaged part CS 152 L1 The MIPS ISA Teams of 4 5 students UC Regents Fall 2006 UCB CS 152 Real hardware not simulation Will we be fabricate CPU dies Back when I was taking classes 1984 Caltech our project course did fab chips Intel XScale 80200 used in earlier HP PocketPCs CS 152 L1 The MIPS ISA UC Regents Fall 2006 UCB FPGAs Field Programmable Gate Arrays Xilinx Virtex E 43 200 parts 655 000 RAM bits Write Verilog to wire parts CS 152 L1 The MIPS ISA UC Regents Fall 2006 UCB Calinx 150 152 boards in 125 Cory Download CPU machine code using TFTP DRAM Xilinx Virtex E FPGA Program Xilinx via PC CS 152 L1 The MIPS ISA UC Regents Fall 2006 UCB Now a GameBoy Advance cartridge Xilinx Sparta n FPGA 50 000 gates Seen at a Los Altos Hills Boy Scout CS 152 L1 The MIPS ISA 16 MB SDRA M on the back side UC Regents Fall 2006 UCB CS 150 is a hard prerequisite for CS152 Exceptions considered only for graduate students CS 152 L1 The MIPS ISA UC Regents Fall 2006 UCB One slide descriptions of CPU projects Final Project 5 weeks Pipelined CPU 3 weeks Single cycle CPU project 3 weeks CS 152 L1 The MIPS ISA UC Regents Fall 2006 UCB Lab 2 Single Cycle CPU 8 29 to 9 25 32 PC 32 D Instr Mem 32 Q 32 32 Addr 32 Data To rs1 rs2 ws op decode logic 0x4 Logic op 5 5 5 32 ws 32 wd 32 CS 152 L1 The MIPS ISA 32 RegFile rs1 rd1 rs2 rd2 32 A L U 32 WE UC Regents Fall 2006 UCB Lab 3 Pipelined CPU 9 26 to 10 16 1 2 IF Stage Instr ID RF Stage Decode Reg Fetch Fetch IR 3 5 4 EX Stage Executio n IR IR A Y M M MEM WB Write Stage Memory Back WE MemToReg IR Mux Logic R B CS 152 L1 The MIPS ISA UC Regents Fall 2006 UCB Project Caches DRAM 10 17 to 11 20 CS 152 L1 The MIPS ISA UC Regents Fall 2006 UCB This course is not for everyone Note Not a prof John is OK really Typical final project time sheets We estimate our total people hours spent on this project to be near 370 hours CS 152 L1 The MIPS ISA Hours Spent Jill 200 hours Bill 200 hours Joe 100 hours Jack 100 hours UC Regents Fall 2006 UCB Can t labs be easier but still worthwhile The labs and project teach you how to design two types of structures Pipelines Work on many instructions at the same time and always get the right answer Caches A slow big memory looks like a fast big memory most of the time and always maintain correct state You only really understand these techniques after you make hardware do them The first time you try it CS 152 L1 The MIPS ISA UC Regents Fall 2006 UCB From a Fall 05 Final Project Presentation And in conclusion Make the lab your home Because it will be Team Projects 4 5 Students CS 152 L1 The MIPS ISA UC Regents Fall 2006 UCB From a Spr 05 Final Project Talk this group had good team dynamics Members Michael Bryant Udam Daniel But what if a teammate is like this In Lab 3 Pat did not perform to his capability Besides not making it to most of the meetings and not completing his work on time the work he did do I ended up redoing anyways Often Pat did other work slept or played games while the rest of us were trying to get the processor working CS 152 L1 The MIPS ISA UC Regents Fall 2006 UCB In Final Project Pat did a better job Pat s Final Project reviews There was a vast improvement in terms of cooperation and involvement What amazed the other teammates and I was that Pat wrote the cache controller and tested it all by himself which none of us knew that he was capable of Why the change CS 152 L1 The MIPS ISA UC Regents Fall 2006 UCB Peer Reviews 20 of final grade Next evaluate the performance of the other members of your group do not evaluate yourself Express your evaluation as a percentage between 0 and 100 A score of 100 indicates that the person met your expectations for a good group member A score of less than 100 indicates that you feel that the group member did not fully live up to the social contract that comes along with enrolling in a team project course in EECS at Cal CS 152 L1 The MIPS ISA UC Regents Fall 2006 UCB 152 Semester Calendar See class webpage for most up to date version www inst eecs berkeley edu cs152 CS 152 L1 The MIPS ISA UC Regents Fall 2006 UCB Week One You are here Download Lab 1 done individually It is a refresher lab for MIPS assembly language programming Use 125 or 119 Cory or use RDF see web page Resources Lab due Tuesday CS 152 L1 The MIPS ISA UC Regents Fall 2006 UCB Week One Preparing for team labs Lab 2 the first team lab is up On Friday meet in your TAs in 125 Cory at your group s section time Decide on a group name during this meeting or beforehand TAs Udam Saini and Jue Sun A team CS152 alumni See web page for contact info CS 152 L1 The MIPS ISA UC Regents Fall 2006 UCB Weeks Two and Three Lab 2 Begins CS 152 L1 The MIPS ISA UC Regents Fall 2006 UCB Week Four Five Lab 2 Ends Begin Lab 3 CS 152 L1 The MIPS ISA UC Regents Fall 2006 UCB Recent history of CS 152 Failed projects In Fall 04 and Spring 05 many groups didn t get their final project CPU working 80 didn t work in Fall 04 50 didn t work in Spring 05 In Fall 05 all groups got their final project working in hardware some did not pass all tests Our goal for Fall 06 All projects successful We want every group to get every CPU working CS 152 L1 The MIPS ISA UC Regents Fall 2006 UCB Recent history of CS 152 Flaky Teammates Most semesters at least one group is disappointed with the work ethic of one of their teammates Our goal for Fall 06 All teammates are good teammates Dysfunctional groups take the fun out of the class …
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