CS 152 Computer Architecture and Engineering Lecture 6 - MemoryLast time in Lecture 5CPU-Memory BottleneckCore MemorySemiconductor Memory, DRAMOne Transistor Dynamic RAMDRAM ArchitectureDRAM PackagingDRAM OperationDouble-Data Rate (DDR2) DRAMPowerPoint PresentationTypical Memory Reference PatternsCommon Predictable PatternsMemory Reference PatternsMultilevel MemoryMemory HierarchyRelative Memory Cell SizesManagement of Memory HierarchyCS152 AdministriviaCachesInside a CacheCache Algorithm (Read)Placement PolicyDirect-Mapped CacheDirect Map Address Selection higher-order vs. lower-order address bits2-Way Set-Associative CacheFully Associative CacheReplacement PolicyAcknowledgementsCS 152 Computer Architecture and Engineering Lecture 6 - MemoryKrste AsanovicElectrical Engineering and Computer SciencesUniversity of California at Berkeleyhttp://www.eecs.berkeley.edu/~krstehttp://inst.eecs.berkeley.edu/~cs1522/10/2009 CS152-Spring’092Last time in Lecture 5•Control hazards (branches, interrupts) are most difficult to handle as they change which instruction should be executed next•Speculation commonly used to reduce effect of control hazards (predict sequential fetch, predict no exceptions)•Branch delay slots make control hazard visible to software•Precise exceptions: stop cleanly on one instruction, all previous instructions completed, no following instructions have changed architectural state•To implement precise exceptions in pipeline, shift faulting instructions down pipeline to “commit” point, where exceptions are handled in program order2/10/2009 CS152-Spring’093CPU-Memory BottleneckMemoryCPUPerformance of high-speed computers is usuallylimited by memory bandwidth & latency• Latency (time for a single access)Memory access time >> Processor cycle time• Bandwidth (number of accesses per unit time)if fraction m of instructions access memory,1+m memory references / instructionCPI = 1 requires 1+m memory refs / cycle(assuming MIPS RISC ISA)2/10/2009 CS152-Spring’094Core Memory•Core memory was first large scale reliable main memory–invented by Forrester in late 40s/early 50s at MIT for Whirlwind project•Bits stored as magnetization polarity on small ferrite cores threaded onto 2 dimensional grid of wires•Coincident current pulses on X and Y wires would write cell and also sense original state (destructive reads)DEC PDP-8/E Board, 4K words x 12 bits, (1968)•Robust, non-volatile storage•Used on space shuttle computers until recently•Cores threaded onto wires by hand (25 billion a year at peak production)•Core access time ~ 1s2/10/2009 CS152-Spring’095Semiconductor Memory, DRAM•Semiconductor memory began to be competitive in early 1970s–Intel formed to exploit market for semiconductor memory•First commercial DRAM was Intel 1103–1Kbit of storage on single chip–charge on a capacitor used to hold value•Semiconductor memory quickly replaced core in ‘70s2/10/2009 CS152-Spring’096One Transistor Dynamic RAMTiN top electrode (VREF)Ta2O5 dielectricW bottomelectrodepolywordlineaccess transistor1-T DRAM Cellwordbitaccess transistorStoragecapacitor (FET gate, trench, stack)VREF2/10/2009 CS152-Spring’097DRAM ArchitectureRow Address DecoderCol.1Col.2MRow 1Row 2NColumn Decoder & Sense AmplifiersMNN+Mbit linesword linesMemory cell(one bit)DData• Bits stored in 2-dimensional arrays on chip• Modern chips have around 4 logical banks on each chip– each logical bank physically implemented as many smaller arrays2/10/2009 CS152-Spring’098DRAM Packaging•DIMM (Dual Inline Memory Module) contains multiple chips with clock/control/address signals connected in parallel (sometimes need buffers to drive signals to all chips)•Data pins work together to return wide word (e.g., 64-bit data bus using 16x4-bit parts)Address lines multiplexed row/column addressClock and control signalsData bus(4b,8b,16b,32b)DRAM chip~12~72/10/2009 CS152-Spring’099DRAM OperationThree steps in read/write access to a given bank•Row access (RAS)–decode row address, enable addressed row (often multiple Kb in row)–bitlines share charge with storage cell–small change in voltage detected by sense amplifiers which latch whole row of bits–sense amplifiers drive bitlines full rail to recharge storage cells•Column access (CAS)–decode column address to select small number of sense amplifier latches (4, 8, 16, or 32 bits depending on DRAM package)–on read, send latched bits out to chip pins–on write, change sense amplifier latches which then charge storage cells to required value–can perform multiple column accesses on same row without another row access (burst mode)•Precharge–charges bit lines to known value, required before next row accessEach step has a latency of around 15-20ns in modern DRAMsVarious DRAM standards (DDR, RDRAM) have different ways of encoding the signals for transmission to the DRAM, but all share same core architecture2/10/2009 CS152-Spring’0910Double-Data Rate (DDR2) DRAM[ Micron, 256Mb DDR2 SDRAM datasheet ]Row Column Precharge Row’Data200MHz Clock400Mb/s Data Rate2/10/2009 CS152-Spring’0911Processor-DRAM Gap (latency)TimeµProc 60%/yearDRAM7%/year110100100019801981198319841985198619871988198919901991199219931994199519961997199819992000DRAMCPU1982Processor-MemoryPerformance Gap:(grows 50% / year)Performance“Moore’s Law”Four-issue 2GHz superscalar accessing 100ns DRAM could execute 800 instructions during time for one memory access!2/10/2009 CS152-Spring’09Typical Memory Reference PatternsAddressTimeInstruction fetchesStackaccessesDataaccessesn loop iterationssubroutine callsubroutine returnargument accessvector accessscalar accesses2/10/2009 CS152-Spring’09Common Predictable PatternsTwo predictable properties of memory references:–Temporal Locality: If a location is referenced it is likely to be referenced again in the near future.–Spatial Locality: If a location is referenced it is likely that locations near it will be referenced in the near future.Memory Reference PatternsDonald J. Hatfield, Jeanette Gerald: Program Restructuring for Virtual Memory. IBM Systems Journal 10(3): 168-192 (1971)TimeMemory Address (one dot per access)SpatialLocalityTemporal Locality2/10/2009 CS152-Spring’09Multilevel MemoryStrategy: Reduce average latency using small, fast memories called caches.Caches are a mechanism to reduce memory latency based on the empirical observation that the patterns of memory references made
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