CS 152 Computer Architecture and Engineering Lecture 9 Designing a Multicycle ProcessorRecap: Processor Design is a ProcessRecap: A Single Cycle DatapathRecap: The “Truth Table” for the Main ControlRecap: PLA Implementation of the Main ControlRecap: Systematic Generation of ControlThe Big Picture: Where are We Now?Behavioral models of Datapath ComponentsBehavioral Specification of Control LogicAbstract View of our single cycle processorWhat’s wrong with our CPI=1 processor?Memory Access TimeReducing Cycle TimeBasic Limits on Cycle TimePartitioning the CPI=1 DatapathExample Multicycle DatapathAdministrative IssuesRecall: Step-by-step Processor DesignStep 4: R-rtype (add, sub, . . .)Step 4: Logical immedStep 4 : LoadStep 4 : StoreStep 4 : BranchAlternative datapath (book): Multiple Cycle DatapathOur Control ModelStep 4 Control Specification for multicycle procTraditional FSM ControllerStep 5 (datapath + state diagram control)Mapping RTs to Control PointsAssigning States(Mostly) Detailed Control Specification (missing0)Performance EvaluationController DesignExample: Jump-CounterUsing a Jump CounterOur MicrosequencerMicroprogram Control SpecificationMapping ROMExample: Controlling MemoryController handles non-ideal memoryReally Simple Time-State ControlTime-state Control PathOverview of ControlSummarySummary (cont’d)Where to get more information?9/28/01 ©UCB Fall 2001CS152 / Kubiatowicz Lec9.1CS 152Computer Architecture and EngineeringLecture 9 Designing a Multicycle ProcessorFebruary 15, 2001John Kubiatowicz (http.cs.berkeley.edu/~kubitron)lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/9/28/01 ©UCB Fall 2001CS152 / Kubiatowicz Lec9.2Recap: Processor Design is a Process°Bottom-up•assemble components in target technology to establish critical timing°Top-down•specify component behavior from high-level requirements°Iterative refinement•establish partial solution, expand and improvedatapathcontrolprocessorInstruction SetArchitectureReg. File Mux ALU Reg Mem Decoder SequencerCells Gates9/28/01 ©UCB Fall 2001CS152 / Kubiatowicz Lec9.3Recap: A Single Cycle Datapath32ALUctrClkbusWRegWr3232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDstExtenderMuxMux3216imm16ALUSrcExtOpMuxMemtoRegClkData InWrEn32AdrDataMemory32MemWrALUInstructionFetch UnitClkEqualInstruction<31:0>010101<21:25><16:20><11:15><0:15>Imm16RdRsRtnPC_sel9/28/01 ©UCB Fall 2001CS152 / Kubiatowicz Lec9.4Recap: The “Truth Table” for the Main ControlR-type ori lw sw beq jumpRegDstALUSrcMemtoRegRegWriteMemWriteBranchJumpExtOpALUop (Symbolic)1001000x“R-type”01010000Or01110001Addx1x01001Addx0x0010xSubtractxxx0001xxxxop 00 0000 00 1101 10 0011 10 1011 00 0100 00 0010ALUop <2> 1 0 0 00xALUop <1> 0 1 0 00xALUop <0> 0 0 0 01xMainControlop6ALUControl(Local)func36ALUopALUctr3RegDstALUSrc:9/28/01 ©UCB Fall 2001CS152 / Kubiatowicz Lec9.5Recap: PLA Implementation of the Main Controlop<0>op<5>..op<5>..<0>op<5>..<0>op<5>..<0>op<5>..<0>op<5>..<0>R-type ori lw sw beq jumpRegWriteALUSrcMemtoRegMemWriteBranchJumpRegDstExtOpALUop<2>ALUop<1>ALUop<0>9/28/01 ©UCB Fall 2001CS152 / Kubiatowicz Lec9.6Recap: Systematic Generation of Control°In our single-cycle processor, each instruction is realized by exactly one control command or “micr oinstruction”•in general, the controller is a finite state machine•microinstruction can also control sequencing (see later)Control Logic / Store(PLA, ROM)OPcodeDatapathInstructionDecodeConditionsControlPointsmicroinstruction9/28/01 ©UCB Fall 2001CS152 / Kubiatowicz Lec9.7The Big Picture: Where are We Now? °The Five Classic Components of a Computer°Today’s Topic: Designing the Datapath for the Multiple Clock Cycle DatapathControlDatapathMemoryProcessorInputOutput9/28/01 ©UCB Fall 2001CS152 / Kubiatowicz Lec9.8Behavioral models of Datapath Componentsentity adder16 isgeneric (ccOut_delay : TIME := 12 ns; adderOut_delay: TIME := 12 ns);port(A, B: in vlbit_1d(15 downto 0); DOUT: out vlbit_1d(15 downto 0); CIN: in vlbit; COUT: out vlbit);end adder16;architecture behavior of adder32 isbeginadder16_process: process(A, B, CIN)variable tmp : vlbit_1d(18 downto 0);variable adder_out : vlbit_1d(31 downto 0);variable carry: vlbit;begintmp := addum (addum (A, B), CIN); adder_out := tmp(15 downto 0);carry :=tmp(16);COUT <= carry after ccOut_delay; DOUT <= adder_out after adderOut_delay; end process;end behavior;161616A BDOUTCinCout9/28/01 ©UCB Fall 2001CS152 / Kubiatowicz Lec9.9Behavioral Specification of Control Logic°Decode / Control-store address modeled by Case statement°Each arm of case drives control signals for that operation•just like the microinstruction•either can be symbolicentity maincontrol isport(opcode: in vlbit_1d(5 downto 0); equal_cond: in vlbit;extop out vlbit;ALUsrc out vlbit;ALUop out vlbit_1d(1 downto 0);MEMwr out vlbit;MemtoReg out vlbit;RegWr out vlbit;RegDst out vlbit;nPC out vlbit;end maincontrol;architecture behavior of maincontrol isbegin control: process(opcode,equal_cond) constant ORIop: vlbit_ld(5 downto 0) := “001101”; begin -- extop only 0 (no extend) for ORI inst case opcode iswhen ORIop => extop <= 0; when others => extop <= 1;end case; end process;end behavior;9/28/01 ©UCB Fall 2001CS152 / Kubiatowicz Lec9.10Abstract View of our single cycle processor°looks like a FSM with PC as statePCNext PCRegisterFetchALUReg. WrtMemAccessDataMemInstructionFetchResult StoreALUctrRegDstALUSrcExtOpMemWrEqualnPC_selRegWrMemWrMemRdMainControlALUcontrolopfunExt9/28/01 ©UCB Fall 2001CS152 / Kubiatowicz Lec9.11What’s wrong with our CPI=1 processor?°Long Cycle Time°All instructions take as much time as the slowest°Real memory is not as nice as our idealized memory•cannot always get the job done in one (short) cyclePC Inst MemorymuxALU Data MemmuxPC Reg FileInst MemorymuxALUmuxPC Inst MemorymuxALU Data MemPC Inst Memory cmpmuxReg FileReg FileReg FileArithmetic & LogicalLoadStoreBranchCritical Pathsetupsetup9/28/01 ©UCB Fall 2001CS152 / Kubiatowicz Lec9.12Memory Access Time°Physics => fast memories are small (large memories are slow)•question: register file vs. memory°=> Use a hierarchy of memoriesStorage Arrayselected word lineaddressstorage cellbit linesense ampsaddressdecoderCacheProcessor1 time-periodproc. busL2Cachemem. bus2-3 time-periods20 - 50 time-periodsmemory9/28/01 ©UCB Fall 2001CS152 /
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