CS 152 Computer Architecture and Engineering Lecture 9 Designing a Multicycle Processor February 15 2001 John Kubiatowicz http cs berkeley edu kubitron lecture slides http www inst eecs berkeley edu cs152 9 28 01 UCB Fall 2001 CS152 Kubiatowicz Recap Processor Design is a Process Bottom up assemble components in target technology to establish critical timing Top down specify component behavior from high level requirements Iterative refinement establish partial solution expand and improve Instruction Set Architecture processor datapath Reg File Mux ALU control Reg Cells 9 28 01 Mem Decoder Sequencer Gates UCB Fall 2001 CS152 Kubiatowicz Recap A Single Cycle Datapath Instruction 31 0 1 Mux 0 RegWr 5 5 Rs 5 Rt Rt ALUctr busA 0 1 32 Imm16 MemtoReg Data In 32 ALUSrc 0 32 Clk WrEn Adr 32 Mux 16 Extender imm16 32 Mux 32 Clk Rw Ra Rb 32 32 bit Registers busB 32 Rd Equal MemWr ALU busW Rs 0 15 Clk 11 15 RegDst Rt 21 25 Rd Instruction Fetch Unit 16 20 nPC sel 1 Data Memory ExtOp 9 28 01 UCB Fall 2001 CS152 Kubiatowicz Recap The Truth Table for the Main Control op 6 Main Control RegDst ALUSrc func 6 ALUop ALU Control Local ALUctr 3 3 op RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUop Symbolic ALUop 2 ALUop 1 ALUop 0 9 28 01 00 0000 R type 1 0 0 1 0 0 0 x R type 1 0 0 00 1101 10 0011 10 1011 00 0100 00 0010 ori lw sw beq jump 0 0 x x x 1 1 1 0 x 0 1 x x x 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 x x Or Add Add Subtract xxx 0 0 0 x 0 1 0 0 x 0 0 0 0 x 1 UCB Fall 2001 CS152 Kubiatowicz Recap PLA Implementation of the Main Control op 5 op 5 0 R type op 5 0 ori op 5 0 lw op 5 0 sw op 5 0 beq jump op 0 RegWrite ALUSrc RegDst MemtoReg MemWrite Branch Jump ExtOp ALUop 2 ALUop 1 ALUop 0 9 28 01 UCB Fall 2001 CS152 Kubiatowicz Recap Systematic Generation of Control Control Logic Store PLA ROM microinstruction Conditions Instruction Decode OPcode Control Points Datapath In our single cycle processor each instruction is realized by exactly one control command or microinstruction in general the controller is a finite state machine microinstruction can also control sequencing see later 9 28 01 UCB Fall 2001 CS152 Kubiatowicz The Big Picture Where are We Now The Five Classic Components of a Computer Processor Input Control Memory Datapath Output Today s Topic Designing the Datapath for the Multiple Clock Cycle Datapath 9 28 01 UCB Fall 2001 CS152 Kubiatowicz Behavioral models of Datapath Components entity adder16 is generic ccOut delay TIME 12 ns adderOut delay TIME 12 ns port A B in vlbit 1d 15 downto 0 DOUT out vlbit 1d 15 downto 0 CIN in vlbit COUT out vlbit end adder16 A 16 Cout Cin 16 DOUT 9 28 01 variable tmp vlbit 1d 18 downto 0 variable adder out vlbit 1d 31 downto 0 variable carry vlbit B 16 architecture behavior of adder32 is begin adder16 process process A B CIN begin tmp addum addum A B CIN adder out tmp 15 downto 0 carry tmp 16 COUT carry after ccOut delay DOUT adder out after adderOut delay end process end behavior UCB Fall 2001 CS152 Kubiatowicz Behavioral Specification of Control Logic entity maincontrol is port opcode in vlbit 1d 5 downto 0 equal cond in vlbit extop ALUsrc ALUop MEMwr MemtoReg RegWr RegDst nPC end maincontrol architecture behavior of maincontrol is out vlbit begin out vlbit control process opcode equal cond out vlbit 1d 1 downto 0 constant ORIop vlbit ld 5 downto 0 001101 out vlbit begin out vlbit extop only 0 no extend for ORI inst out vlbit case opcode is out vlbit when ORIop extop 0 out vlbit when others extop 1 end case end process end behavior Decode Control store address modeled by Case statement Each arm of case drives control signals for that operation just like the microinstruction 9 28 01 either can be symbolic UCB Fall 2001 CS152 Kubiatowicz Abstract View of our single cycle processor Main Control op Result Store MemWr RegDst RegWr Reg Wrt Data Mem Mem Access Ext ExtOp ALUSrc ALUctr Equal Register Fetch Instruction Fetch PC nPC sel Next PC ALU MemRd MemWr ALU control fun looks like a FSM with PC as state 9 28 01 UCB Fall 2001 CS152 Kubiatowicz What s wrong with our CPI 1 processor Arithmetic Logical PC Inst Memory Reg File mux ALU mux setup Load PC Inst Memory ALU Data Mem Store PC mux Reg File Critical Path Inst Memory Reg File ALU Data Mem Branch PC Inst Memory Reg File mux cmp mux setup mux Long Cycle Time All instructions take as much time as the slowest Real memory is not as nice as our idealized memory cannot always get the job done in one short cycle 9 28 01 UCB Fall 2001 CS152 Kubiatowicz Memory Access Time Physics fast memories are small large memories are slow Storage Array selected word line storage cell address bit line address decoder sense amps Processor Cache proc bus Use a hierarchy of memories L2 Cache 1 time period 2 3 time periods 9 28 01 UCB Fall 2001 mem bus question register file vs memory memory 20 50 time periods CS152 Kubiatowicz Reducing Cycle Time Cut combinational dependency graph and insert register latch Do same work in two fast cycles rather than one slow one May be able to short circuit path and remove some components for some instructions storage element storage element Acyclic Combinational Logic Acyclic Combinational Logic A storage element Acyclic Combinational Logic B storage element 9 28 01 UCB Fall 2001 storage element CS152 Kubiatowicz Basic Limits on Cycle Time Next address logic PC branch PC offset PC 4 Instruction Fetch InstructionReg Mem PC Register Access A R rs ALU operation UCB Fall 2001 Result Store MemWr RegDst RegWr Reg File Data Mem MemRd MemWr ALUctr Exec Mem Access Operand Fetch Instruction Fetch PC ExtOp nPC sel Next PC 9 28 01 ALUSrc Control R A B CS152 Kubiatowicz 9 28 01 UCB Fall 2001 Place enables on all registers Result Store MemWr MemRd MemWr RegDst RegWr Reg File Data Mem Exec Mem Access ALUctr ALUSrc ExtOp Operand Fetch Instruction Fetch PC Next PC nPC sel Equal Partitioning the CPI 1 Datapath Add registers between smallest steps CS152 Kubiatowicz 9 28 01 ExtOp Equal B UCB Fall 2001 S Reg File RegDst RegWr MemToReg MemRd MemWr ALUctr Ext ALUSrc ALU A Result Store Reg File Mem Access IR nPC sel E Data Mem Operand Fetch Instruction Fetch PC Next PC Example Multicycle Datapath M Critical Path CS152 Kubiatowicz Administrative Issues Read Chapter 5 This lecture and next one slightly different from the book Mostly picked groups yesterday Pick permanent section Groups must be within section If you don t have a …
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