CS 152 Computer Architecture andEngineering Lecture 3 - From CISC to RISCKrste AsanovicElectrical Engineering and Computer SciencesUniversity of California at Berkeleyhttp://www.eecs.be rkeley.edu /~krstehttp://inst.eecs.b erkeley.ed u/~cs1521/31/2008 CS152-Spring!082Last Time in Lecture 2• Stack machines popular to simplify High-LevelLanguage (HLL) implementation– Algol-68 & Burroughs B5000, Forth machines, Occam & Transputers,Java VMs & Java Interpreters• General-purpose register machines provide greaterefficiency with better compiler technology (or assemblycoding)– Compilers can explicity manage fastest level of memory hierarchy(registers)• Microcoding was a straightforward way to implementsimple machines with low gate count– But also allowed arbitrary instruction complexity as microcode storesgrew– Makes most sense when fast read-only memory (ROM) significantlyfaster than read-write memory (RAM)1/31/2008 CS152-Spring!083Microprogramming thrived in theSeventies• Significantly faster ROMs than DRAMs/core wereavailable• For complex instruction sets (CISC), datapath andcontroller were cheaper and simpler• New instructions , e.g., floating point, could besupported without datapath modifications• Fixing bugs in the controller was easier• ISA compatibility across various models could beachieved easily and cheaplyExcept for the cheapest and fastest machines,all computers were microprogrammed1/31/2008 CS152-Spring!084 Writable Control Store (WCS)• Implement control store in RAM not ROM– MOS SRAM memories now became almost as fast as control store(core memories/DRAMs were 2-10x slower)– Bug-free microprograms difficult to write• User-WCS provided as option on several minicomputers– Allowed users to change microcode for each processor• User-WCS failed– Little or no programming tools support– Difficult to fit software into small space– Microcode control tailored to original ISA, less useful for others– Large WCS part of processor state - expensive context switches– Protection difficult if user can change microcode– Virtual memory required restartable microcode1/31/2008 CS152-Spring!085Microprogramming: early Eighties• Evolution bred more complex micro-machines– CISC ISAs led to need for subroutine and call stacks in !code– Need for fixing bugs in control programs was in conflict with read-onlynature of !ROM– --> WCS (B1700, QMachine, Intel i432, …)• With the advent of VLSI technology assumptions aboutROM & RAM speed became invalid -> more complexity• Better compilers made complex instructions lessimportant• Use of numerous micro-architectural innovations, e.g.,pipelining, caches and buffers, made multiple-cycleexecution of reg-reg instructions unattractive1/31/2008 CS152-Spring!086Microprogramming in Modern Usage• Microprogramming is far from extinct• Played a crucial role in micros of the EightiesDEC uVAX, Motorola 68K series, Intel 386 and 486• Microcode pays an assisting role in most modernmicros (AMD Athlon, Intel Core 2 Duo, IBM PowerPC)• Most instructions are executed directly, i.e., with hard-wired control• Infrequently-used and/or complicated instructions invoke the microcode engine• Patchable microcode common for post-fabrication bug fixes, e.g. Intel Pentiums load !code patches at bootup1/31/2008 CS152-Spring!087From CISC to RISC• Use fast RAM to build fast instruction cache of user-visible instructions, not fixed hardware microroutines– Can change contents of fast instruction memory to fit whatapplication needs right now• Use simple ISA to enable hardwired pipelinedimplementation– Most compiled code only used a few of the available CISCinstructions– Simpler encoding allowed pipelined implementations• Further benefit with integration– In early ‘80s, can fit 32-bit datapath + small caches on a single chip– No chip crossings in common case allows faster operation1/31/2008 CS152-Spring!088Horizontal vs Vertical µCode• Horizontal µcode has wider µinstructions– Multiple parallel operations per µinstruction– Fewer steps per macroinstruction– Sparser encoding ! more bits• Vertical µcode has narrower µinstructions– Typically a single datapath operation per µinstruction– separate µinstruction for branches– More steps to per macroinstruction– More compact ! less bits• Nanocoding– Tries to combine best of horizontal and vertical µcode# µInstructionsBits per µInstruction1/31/2008 CS152-Spring!089Nanocoding• MC68000 had 17-bit µcode containing either 10-bit µjump or 9-bitnanoinstruction pointer– Nanoinstructions were 68 bits wide, decoded to give 196 controlsignalsµcode ROMnanoaddressµcodenext-stateµaddressµPC (state)nanoinstruction ROMdataExploits recurringcontrol signal patternsin µcode, e.g.,ALU0A " Reg[rs]...ALUi0A " Reg[rs]...User PCInst. CacheHardwired Decode1/31/2008 CS152-Spring!0810CDC 6600 Seymour Cray, 1964• A fast pipelined machine with 60-bit words• Ten functional units- Floating Point: adder, multiplier, divider- Integer: adder, multiplier...• Hardwired control (no microcoding)• Dynamic scheduling of instructions using a scoreboard• Ten Peripheral Processors for Input/Output - a fast time-shared 12-bit integer ALU• Very fast clock, 10MHz• Novel freon-based technology for cooling1/31/2008 CS152-Spring!0811CDC 6600: DatapathAddress Regs Index Regs 8 x 18-bit 8 x 18-bitOperand Regs8 x 60-bitInst. Stack8 x 60-bitIR10 FunctionalUnitsCentralMemory128K words,32 banks,1µs cycleresultaddrresultoperandoperandaddr1/31/2008 CS152-Spring!0812• Separate instructions to manipulate three types of reg.8 60-bit data registers (X)8 18-bit address registers (A)8 18-bit index registers (B)• All arithmetic and logic instructions are reg-to-reg • Only Load and Store instructions refer to memory!Touching address registers 1 to 5 initiates a load 6 to 7 initiates a store - very useful for vector operations 6 3 3 3 opcode i j k Ri " (Rj) op (Rk)CDC 6600:A Load/Store Architecture 6 3 3 18 opcode i j disp Ri " M[(Rj) + disp]1/31/2008 CS152-Spring!0813CDC6600: Vector AdditionB0 " - nloop: JZE B0, exitA0 " B0 + a0 load X0A1 " B0 + b0 load X1X6 " X0 + X1A6 " B0 + c0 store X6B0 " B0 + 1jump loopAi = address registerBi = index registerXi = data register1/31/2008 CS152-Spring!0814CDC6600 ISA
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