CS152 Computer Architecture and Engineering Fall 2004 Lecture 10 Basic MIPS Pipelining Review John Lazzaro www cs berkeley edu lazzaro Dave Patterson www cs berkeley edu patterson Adapted from Mary Jane Irwin s slides www cse psu edu cg431 CS 152 L10 Pipeline Intro 1 Fall 2004 UC Regents Recap last lecture Customers measure to buy Architects measure for design Tools Performance Equation CPI Seconds Program Instructions Cycles Seconds Program Instruction Cycle Amdahl s Law s lesson Balance Speedupwhole 1 1 affected Speeduppart Energy E0 1 21 CS 152 L10 Pipeline Intro 2 C 2 Vdd E1 0 2 1 C 2 Vdd Fall 2004 UC Regents The Five Stages of Load Instruction Cycle 1 Cycle 2 lw IFetch Dec Cycle 3 Cycle 4 Cycle 5 Exec Mem WB IFetch Instruction Fetch and Update PC Dec Registers Fetch and Instruction Decode Exec Execute R type calculate memory address Mem Read write the data from to the Data Memory WB Write the result data into the register file CS 152 L10 Pipeline Intro 3 Fall 2004 UC Regents Pipelined MIPS Processor Start the next instruction while still working on the current one improves throughput or bandwidth total amount of work done in a given time average instructions per second or per clock instruction latency is not reduced time from the start of an instruction to its completion Cycle 1 Cycle 2 IFetch Dec lw Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Exec IFetch Dec sw R type Mem WB Exec Mem WB Exec Mem IFetch Dec WB pipeline clock cycle pipeline stage time is limited by the slowest stage for some instructions some stages are wasted cycles CS 152 L10 Pipeline Intro 4 Fall 2004 UC Regents Single Cycle Multiple Cycle vs Pipeline Single Cycle Implementation Cycle 1 Clk Cycle 2 Load Store Waste Multiple Cycle Implementation Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9Cycle 10 Clk lw IFetch Dec Exec Mem WB sw IFetch Dec Pipeline Implementation lw IFetch sw Exec Mem WB IFetch Dec Exec Mem WB Dec Exec Mem CS 152 L10 Pipeline Intro 5 Mem wasted cycles Dec R type IFetch Exec R type IFetch WB Fall 2004 UC Regents Multiple Cycle v Pipeline Bandwidth v Latency Multiple Cycle Implementation Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9Cycle 10 Clk lw IFetch Dec Exec Mem WB sw IFetch Dec Exec Mem R type IFetch Pipeline Implementation lw IFetch sw Dec Exec Mem WB IFetch Dec Exec Mem WB Dec Exec Mem R type IFetch WB Latency per lw 5 clock cycles for both Bandwidth of lw is 1 per clock clock IPC for pipeline vs 1 5 IPC for multicycle Pipelining improves instruction bandwidth not instruction latency CS 152 L10 Pipeline Intro 6 Fall 2004 UC Regents Pipelining the MIPS ISA What makes it easy all instructions are the same length 32 bits easier to fetch in 1st stage and decode in 2nd stage few instruction formats three with symmetry across formats can begin reading register file in 2 nd stage memory operations can occur only in loads and stores can use the execute stage to calculate memory addresses each MIPS instruction writes at most one result and does so near the end of the pipeline What makes it hard structural hazards what if we had only one memory control hazards what about branches data hazards what if an instruction s input operands depend on the output of a previous instruction CS 152 L10 Pipeline Intro 7 Fall 2004 UC Regents MIPS Pipeline Datapath Modifications What do we need to add modify in our MIPS datapath registers between pipeline stages to isolate them IF IFetch ID Dec EX Execute MEM MemAccess 1 WB WriteBack 0 Add Shift left 2 Read Addr 2Data 1 File Write Addr Write Data 16 Sign Extend Read Data 2 0 1 ALU Exec Mem Register Read Dec Exec Read Address Read Addr 1 IFetch Dec PC Instruction Memory Add Data Memory Address Write Data Read Data Mem WB 4 1 0 32 System Clock CS 152 L10 Pipeline Intro 8 Fall 2004 UC Regents Graphically Representing MIPS Pipeline Reg ALU IM DM Reg Can help with answering questions like how many cycles does it take to execute this code what is the ALU doing during cycle 4 is there a hazard why does it occur and how can it be fixed CS 152 L10 Pipeline Intro 9 Fall 2004 UC Regents Why Pipeline For Throughput Time clock cycles Inst 3 IM Reg DM IM Reg DM IM Reg DM IM Reg ALU Inst 2 DM ALU Inst 1 Once the pipeline is full one instruction is completed every cycle Reg ALU IM ALU O r d e r Inst 0 ALU I n s t r Inst 4 Reg Reg Reg Reg DM Reg Time to fill the pipeline CS 152 L10 Pipeline Intro 10 Fall 2004 UC Regents Administrivia Lab 2 demo Friday due Monday Feedback on team effort How did it work Change before pipeline Reading Chapter 6 sections 6 1 to 6 4 for today 6 5 to 6 9 for next 2 lectures Midterm Tue Oct 12 5 30 8 30 in 101 Morgan you asked for it Northwest corner of campus near Arch and Hearst Midterm review Sunday Oct 10 7 PM 306 Soda Bring 1 page handwritten notes both sides Nothing electronic no calculators cell phones pagers Meet at LaVal s Northside afterwards for Pizza CS 152 L10 Pipeline Intro 11 Fall 2004 UC Regents Important Observation Each functional unit can only be used once per instruction since 4 other instructions executing If each functional unit used at different stages then leads to hazards Load uses Register File s Write Port during its 5th stage R type uses Register File s Write Port during its 4th stage 2 ways to solve this pipeline hazard 1 Load Ifetch 1 R type CS 152 L10 Pipeline Intro 12 Ifetch 2 Reg Dec 2 Reg Dec 3 Exec 4 Mem 3 4 Exec Wr 5 Wr Fall 2004 UC Regents Solution 1 Insert Bubble into the Pipeline Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Clock Ifetch Load Reg Dec Ifetch R type Exec Reg Dec Ifetch R type Wr Exec Mem Reg Dec Exec Ifetch R type Reg Dec Ifetch Wr Wr Pipeline Exec Bubble Reg Dec Ifetch Wr Exec Reg Dec Wr Exec Insert a bubble into the pipeline to prevent 2 writes at the same cycle The control logic can be complex Lose instruction fetch and issue opportunity No instruction is started in Cycle 6 CS 152 L10 Pipeline Intro 13 Fall 2004 UC Regents Solution 2 Delay R type s Write by One Cycle Delay R type s register write by one cycle Now R type instructions also use Reg File s write port at Stage 5 Mem stage is a NOP stage nothing is being done 1 R type 3 4 Exec Mem 2 Ifetch Reg Dec Cycle 5 …
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