9/20/01 ©UCB Fall 2001CS152 / Kubiatowicz Lec6.1CS152Computer Architecture and EngineeringLecture 6Divide, Floating Point, Pentium BugSeptember 20, 2001John Kubiatowicz (http.cs.berkeley.edu/~kubitron)lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/9/20/01 ©UCB Fall 2001CS152 /Kubiatowicz Lec6.2Recap of Last Lecture: Summary° Intro to VHDL• entity = symbol, architecture ~ schematic, signals = wires• behavior can be higher level• x <= boolean_expression(A,B,C,D);° On-line Design Notebook• Open a window with editor, or our tool, => cut&paste° Multiply: successive refinement to see final design • 32-bit Adder, 64-bit shift register, 32-bit Multiplicand Register• Booth’s algorithm to handle signed multiplies• There are algorithms that calculate many bits of multiply per cycle (see exercises 4.36 to 4.39 in COD)9/20/01 ©UCB Fall 2001CS152 / Kubiatowicz Lec6.3Recap: VHDL combinational exampleENTITY nandnor isGENERIC (delay: TIME := 1ns);PORT (a,b: IN VLBIT; x,y: OUT VLBIT)END nandnoreARCHITECTURE behavioral OF nandnor isBEGINx <= a NOR b AFTER delay;y <= a NAND x AFTER delay;END behavioral;9/20/01 ©UCB Fall 2001CS152 /Kubiatowicz Lec6.4Review: MULTIPLY HARDWARE Version 3° 32-bit Multiplicand reg, 32-bit ALU, 64-bit Product reg (shift right), (0-bit Multiplier reg)Product(Multiplier)Multiplicand32-bit ALUWriteControl32 bits64 bitsShift Right“HI” “LO”9/20/01 ©UCB Fall 2001CS152 / Kubiatowicz Lec6.5Review: Booth’s Algorithm InsightCurrent Bit Bit to the Right Explanation Example Op1 0 Begins run of 1s 0001111000 sub1 1 Middle of run of 1s 0001111000 none0 1 End of run of 1s 0001111000 add0 0 Middle of run of 0s 0001111000 noneOriginally for Speed (when shift was faster than add)° Replace a string of 1s in multiplier with an initial subtract when we first see a one and then later add for the bit afterthe last one0 1 1 1 1 0beginning of runend of runmiddle of run–1+ 10000011119/20/01 ©UCB Fall 2001CS152 /Kubiatowicz Lec6.6Radix-4 Modified Booth’s AlgorithmCurrent Bit to the Explanation Example RecodeBits Right0 0 0 Middle of zeros 00 00 00 0000 00 1 0 Single one 00 00 00 0100 11 0 0 Begins run of 1s 00 01 11 1000 -21 1 0 Begins run of 1s 00 01 11 1100 -10 0 1 Ends run of 1s 00 0011 11 00 10 1 1 Ends run of 1s 00 0111 11 00 21 0 1 Isolated 0 00 11 1011 00 -11 1 1 Middle of run 00 11 1111 00 0° Same insight as one-bit Booth’s, simply adjust for alignment of 2 bits.° Allows multiplication 2-bits at a time.–1+ 10000011119/20/01 ©UCB Fall 2001CS152 / Kubiatowicz Lec6.7Review: Unsigned Combinational Multiplier° Stage i accumulates A * 2 iif Bi== 1° Q: How much hardware for 32 bit multiplier? Critical path?B0A0A1A2A3A0A1A2A3A0A1A2A3A0A1A2A3B1B2B3P0P1P2P3P4P5P6P700 009/20/01 ©UCB Fall 2001CS152 /Kubiatowicz Lec6.8Carry Save addition of 4 integers° Add Columns first, then rows!° Can be used to reduce critical path of multiply ° Example: 53 bit multiply (for floating point):• At least 53 levels with naïve technique• Only 9 with Carry save addition!Carry Save Adder3=>2I1I2S0S1I3Carry Save Adder3=>2I1I2S0S1I3Carry Save Adder3=>2I1I2S0S1I30C2Carry Save Adder3=>2I1I2S0S1I3Carry Save Adder3=>2I1I2S0S1I3Carry Save Adder3=>2I1I2S0S1I3S0S1S2S3S4Carry Save Adder3=>2I1I2S0S1I3Carry Save Adder3=>2I1I2S0S1I30Carry Save Adder3=>2I1I2S0S1I3B2A2C1B1A1C0B0A0D0D1D29/20/01 ©UCB Fall 2001CS152 / Kubiatowicz Lec6.9Review: Combinational Shifter from MUXes° What comes in the MSBs?° How many levels for 32-bit shifter?° What if we use 4-1 Muxes ?10selABDBasic Building Block8-bit right shifter:101010101010101010101010101010101010101010101010S2S1S0A0A1A2A3A4A5A6A7R0R1R2R3R4R5R6R79/20/01 ©UCB Fall 2001CS152 /Kubiatowicz Lec6.10Funnel ShifterXYR° Shift A by i bits (sa= shift right amount)° Logical: Y = 0, X=A, sa=i° Arithmetic? Y = Sign, X=A, sa=i° Rotate? Y = A, X=A, sa=i° Left shifts? Y = A, X=0, sa=32-iInstead Extract 32 bits of 64.Shift RightShift Right323232YXR9/20/01 ©UCB Fall 2001CS152 / Kubiatowicz Lec6.11Barrel ShifterTechnology-dependent solutions: transistor per switchD3D2D1D0A6A5A4A3 A2 A1 A0SR0SR1SR2SR39/20/01 ©UCB Fall 2001CS152 /Kubiatowicz Lec6.12Divide: Paper & Pencil1001 QuotientDivisor 1000 1001010 Dividend–1000101011010–100010 Remainder (or Modulo result)See how big a number can be subtracted, creating quotient bit on each stepBinary => 1 * divisor or 0 * divisorDividend = Quotient x Divisor + Remainder=> | Dividend | = | Quotient | + | Divisor |3 versions of divide, successive refinement9/20/01 ©UCB Fall 2001CS152 / Kubiatowicz Lec6.13DIVIDE HARDWARE Version 1° 64-bit Divisor reg, 64-bit ALU, 64-bit Remainder reg, 32-bit Quotient regRemainderQuotientDivisor64-bit ALUShift RightShift LeftWriteControl32 bits64 bits64 bits9/20/01 ©UCB Fall 2001CS152 /Kubiatowicz Lec6.142b. Restore the original value by adding the Divisor register to the Remainder register, &place the sum in the Remainder register. Alsoshift the Quotient register to the left, setting the new least significant bit to 0.Divide Algorithm Version 1°Takes n+1 steps for n-bit Quotient & Rem.Remainder Quotient Divisor0000 0111 0000 0010 0000Test RemainderRemainder < 0Remainder t 01. Subtract the Divisor register from the Remainder register, and place the result in the Remainder register.2a. Shift the Quotient register to the left setting the new rightmostbit to 1.3. Shift the Divisor register right1 bit.DoneYes: n+1 repetitions (n = 4 here)Start: Place Dividend in Remaindern+1repetition?No: < n+1 repetitions9/20/01 ©UCB Fall 2001CS152 / Kubiatowicz Lec6.15Divide Algorithm I example (7 / 2)Remainder Quotient Divisor0000 0111 00000 0010 00001: 1110 0111 00000 0010 00002: 0000 0111 00000 0010 00003: 0000 0111 00000 0001 00001: 1111 0111 00000 0001 00002: 0000 0111 00000 0001 00003: 0000 0111 00000 0000 10001: 1111 1111 00000 0000 10002: 0000 0111 00000 0000 10003: 0000 0111 00000 0000 01001: 0000 0011 00000 0000 0100 2: 0000 0011 00001 0000 0100 3: 0000 0011 00001 0000 0010 1: 0000 0001 00001 0000 0010 2: 0000 0001 00011 0000 0010 3: 0000 0001 00011 0000 0010 Answer:Quotient = 3Remainder = 19/20/01 ©UCB Fall 2001CS152 /Kubiatowicz Lec6.16Observations on Divide Version 1° 1/2 bits in divisor always 0=> 1/2 of 64-bit adder is wasted=> 1/2 of divisor is wasted° Instead of shifting divisor to right, shift remainder to left?° 1st
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