Recap of Last Lecture Summary Intro to VHDL entity symbol architecture schematic signals wires CS152 Computer Architecture and Engineering Lecture 6 Divide Floating Point Pentium Bug behavior can be higher level x boolean expression A B C D On line Design Notebook Open a window with editor or our tool cut paste Multiply successive refinement to see final design 32 bit Adder 64 bit shift register 32 bit Multiplicand Register Booth s algorithm to handle signed multiplies September 20 2001 There are algorithms that calculate many bits of multiply per cycle see exercises 4 36 to 4 39 in COD John Kubiatowicz http cs berkeley edu kubitron lecture slides http www inst eecs berkeley edu cs152 9 20 01 UCB Fall 2001 CS152 Kubiatowicz Lec6 1 Recap VHDL combinational example 9 20 01 CS152 Kubiatowicz Lec6 2 UCB Fall 2001 Review MULTIPLY HARDWARE Version 3 32 bit Multiplicand reg 32 bit ALU 64 bit Product reg shift right 0 bit Multiplier reg ENTITY nandnor is GENERIC delay TIME 1ns PORT a b IN VLBIT x y OUT VLBIT END nandnore Multiplicand 32 bits ARCHITECTURE behavioral OF nandnor is BEGIN 32 bit ALU x a NOR b AFTER delay HI y a NAND x AFTER delay END behavioral 9 20 01 LO Shift Right Product Multiplier 64 bits UCB Fall 2001 CS152 Kubiatowicz Lec6 3 9 20 01 Control Write UCB Fall 2001 CS152 Kubiatowicz Lec6 4 Review Booth s Algorithm Insight middle of run end of run Radix 4 Modified Booth s Algorithm beginning of run 0 1 1 1 1 0 Current Bit Bit to the Right Current Bits Bit to the Right Explanation Example Recode 0 00 0 Middle of zeros 00 00 00 00 00 01 0 Single one 00 00 00 01 00 1 Explanation Example Op 10 0 Begins run of 1s 00 01 11 10 00 2 11 0 Begins run of 1s 00 01 11 11 00 1 00 1 Ends run of 1s 00 00 11 11 00 1 1 0 Begins run of 1s 0001111000 sub 1 1 Middle of run of 1s 0001111000 none 0 1 End of run of 1s 0001111000 add 01 1 Ends run of 1s 00 01 11 11 00 2 none 10 1 Isolated 0 00 11 10 11 00 1 11 1 Middle of run 00 11 11 11 00 0 0 0 Middle of run of 0s 0001111000 Originally for Speed when shift was faster than add Replace a string of 1s in multiplier with an initial subtract when we first see a one and then later add for the bit after the last one 9 20 01 1 10000 01111 CS152 Kubiatowicz Lec6 5 UCB Fall 2001 Review Unsigned Combinational Multiplier 0 A3 0 A2 0 A1 A3 A2 A2 A1 A1 A2 A1 9 20 01 C2 B2 A 2 A0 A0 B1 A0 A0 CS152 Kubiatowicz Lec6 6 UCB Fall 2001 Carry Save addition of 4 integers B2 A3 Allows multiplication 2 bits at a time 0 B0 A3 1 10000 01111 Same insight as one bit Booth s simply adjust for alignment of 2 bits B3 Add Columns first then rows I1 I2 C 1 B 1 A1 I3 I1 Carry Save Adder 3 2 Can be used to reduce critical path of multiply S1 Example 53 bit multiply for floating point At least 53 levels with na ve technique Only 9 with Carry save addition I2 C0 B0 A 0 I3 I1 Carry Save Adder 3 2 S0 S1 D2 S0 I1 I2 I3 S1 S0 D0 I1 I2 I3 S1 0 I1 Carry Save Adder 3 2 S0 I3 S1 D1 Carry Save Adder 3 2 I2 Carry Save Adder 3 2 I2 I3 Carry Save Adder 3 2 S0 S1 S0 0 P7 P6 P5 P4 P3 P2 P1 P0 I1 I2 I3 Carry Save Adder 3 2 Stage i accumulates A 2 i if Bi 1 S1 S0 I1 I2 I3 Carry Save Adder 3 2 S1 S0 I1 I2 I3 Carry Save Adder 3 2 S1 S0 Q How much hardware for 32 bit multiplier Critical path 9 20 01 UCB Fall 2001 CS152 Kubiatowicz Lec6 7 9 20 01 S 4 S3 S2 UCB Fall 2001 S1 S0 CS152 Kubiatowicz Lec6 8 Funnel Shifter Review Combinational Shifter from MUXes Basic Building Block sel A B 1 0 Instead Extract 32 bits of 64 Y D 8 bit right shifter A7 A6 A5 A4 A3 A2 A1 X S2 S1 S0 A0 Shift Right 1 1 1 0 1 0 1 0 R7 1 0 1 0 1 0 1 R6 R5 0 1 0 1 0 1 0 1 0 1 0 R4 1 0 1 0 1 0 R3 1 R2 0 1 0 1 0 1 0 1 0 0 1 0 0 R1 1 Shift A by i bits sa shift right amount Logical 0 X 32 X A sa i 32 Shift Right Rotate Y A Left shifts Y A CS152 Kubiatowicz Lec6 9 UCB Fall 2001 Y Arithmetic Y Sign X A sa i R0 What comes in the MSBs How many levels for 32 bit shifter What if we use 4 1 Muxes 9 20 01 Y 0 R X A sa i 32 X 0 sa 32 i 9 20 01 R UCB Fall 2001 CS152 Kubiatowicz Lec6 10 Divide Paper Pencil Barrel Shifter Technology dependent solutions transistor per switch SR3 SR2 SR1 SR0 1001 D3 Divisor 1000 D2 A6 1001010 1000 10 101 1010 1000 10 Quotient Dividend Remainder or Modulo result D1 A5 See how big a number can be subtracted creating quotient bit on each step Binary 1 divisor or 0 divisor D0 A4 Dividend Quotient x Divisor Remainder Dividend Quotient Divisor A3 9 20 01 A2 A1 UCB Fall 2001 A0 3 versions of divide successive refinement CS152 Kubiatowicz Lec6 11 9 20 01 UCB Fall 2001 CS152 Kubiatowicz Lec6 12 DIVIDE HARDWARE Version 1 Divide Algorithm Version 1 Takes n 1 steps for n bit Quotient Rem 64 bit Divisor reg 64 bit ALU 64 bit Remainder reg 32 bit Quotient reg Remainder Quotient Divisor 0000 0111 0000 0010 0000 Start Place Dividend in Remainder 1 Subtract the Divisor register from the Remainder register and place the result in the Remainder register Remainder t 0 Remainder 0 Shift Right Divisor 64 bits Quotient 64 bit ALU Remainder Test Remainder 2a Shift the Quotient register to the left setting the new rightmost bit to 1 Shift Left 32 bits 2b Restore the original value by adding the Divisor register to the Remainder register place the sum in the Remainder register Also shift the Quotient register to the left setting the new least significant bit to 0 3 Shift the Divisor register right1 bit Write Control 64 bits n 1 repetition No n 1 repetitions Yes n 1 repetitions n 4 here 9 20 01 UCB Fall 2001 CS152 Kubiatowicz Lec6 13 Remainder 1 2 3 1 2 3 1 2 3 1 2 3 1 2 3 9 20 01 0111 0111 0111 0111 0111 0111 0111 1111 0111 0111 0011 0011 …
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