CS 152 Computer Architecture and Engineering Lecture 15 Advanced Superscalars Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http www eecs berkeley edu krste http inst eecs berkeley edu cs152 Last time in Lecture 14 Control hazards are serious impediment to superscalar performance Dynamic branch predictors can be quite accurate 95 and avoid most control hazards Branch History Tables BHTs just predict direction later in pipeline Just need a few bits per entry 2 bits gives hysteresis Need to decode instruction bits to determine whether this is a branch and what the target address is Branch Target Buffer BTB predicts whether a branch and target address Needs PC tag predicted Next PC and direction Just needs PC of instruction to predict target of branch if any Return address stack special form of BTB used to predict subroutine return addresses 4 1 2008 CS152 Spring 08 2 Data in ROB Design HP PA8000 Pentium Pro Core2Duo Register File holds only committed state Ins use exec op p1 src1 p2 src2 pd dest data t1 t2 tn Reorder buffer Load Unit FU FU Store Unit FU Commit t result On dispatch into ROB ready sources can be in regfile or in ROB dest copied into src1 src2 if ready before dispatch On completion write to dest field and broadcast to src fields On issue read from ROB src fields 4 1 2008 3 CS152 Spring 08 Unified Physical Register File MIPS R10K Alpha 21264 Pentium 4 r1 r2 ti tj Rename Table t1 t2 tn Snapshots for mispredict recovery Load Unit FU FU FU ROB not shown Reg File FU Store Unit t result One regfile for both committed and speculative values no data in ROB During decode instruction result allocated new physical register source regs translated to physical regs through rename table Instruction reads data from regfile at start of execute not in decode Write back updates reg busy bits on instructions in ROB assoc search Snapshots of rename table taken at every branch to recover mispredicts On exception renaming undone in reverse order of issue MIPS R10000 4 1 2008 CS152 Spring 08 4 Pipeline Design with Physical Regfile Branch Resolution kill Branch Prediction PC Fetch kill kill Decode Rename Update predictors kill Out of Order Reorder Buffer In Order Commit In Order Physical Reg File Branch ALU MEM Unit Store Buffer D Execute 4 1 2008 5 CS152 Spring 08 Lifetime of Physical Registers Physical regfile holds committed and speculative values Physical registers decoupled from ROB entries no data in ROB ld r1 r3 add r3 r1 4 sub r6 r7 r9 add r3 r3 r6 ld r6 r1 add r6 r6 r3 st r6 r1 ld r6 r11 Rename ld P1 Px add P2 P1 4 sub P3 Py Pz add P4 P2 P3 ld P5 P1 add P6 P5 P4 st P6 P1 ld P7 Pw When can we reuse a physical register 4 1 2008 CS152 Spring 08 6 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P7 P5 P6 P0 P1 P2 P3 P4 P5 P6 P7 P8 R6 R7 R3 R1 p p p p p2 Rd Free List P0 P1 P3 P2 P4 ld r1 0 r3 add r3 r1 4 sub r6 r7 r6 add r3 r3 r6 ld r6 0 r1 Pn ROB use ex Physical Regs op p1 PR1 4 1 2008 PR2 LPRd PRd LPRd requires third read port on Rename Table for each instruction 7 CS152 Spring 08 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P0 P7 P5 P6 4 1 2008 P0 P1 P2 P3 P4 P5 P6 P7 P8 R6 R7 R3 R1 p p p p p2 Rd r1 Free List P0 P1 P3 P2 P4 ld r1 0 r3 add r3 r1 4 sub r6 r7 r6 add r3 r3 r6 ld r6 0 r1 Pn ROB use ex x Physical Regs op ld p1 p PR1 P7 PR2 CS152 Spring 08 LPRd P8 PRd P0 8 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P0 P7 P1 P5 P6 P0 P1 P2 P3 P4 P5 P6 P7 P8 R6 R7 R3 R1 p p p p p2 Rd r1 r3 Free List P0 P1 P3 P2 P4 ld r1 0 r3 add r3 r1 4 sub r6 r7 r6 add r3 r3 r6 ld r6 0 r1 Pn ROB use ex x x Physical Regs op p1 ld p add PR1 P7 P0 4 1 2008 PR2 LPRd P8 P7 PRd P0 P1 9 CS152 Spring 08 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P0 P7 P1 P5 P3 P6 4 1 2008 P0 P1 P2 P3 P4 P5 P6 P7 P8 R6 R7 R3 R1 p p p p p2 PR2 p P5 Rd r1 r3 r6 Free List P0 P1 P3 P2 P4 ld r1 0 r3 add r3 r1 4 sub r6 r7 r6 add r3 r3 r6 ld r6 0 r1 Pn ROB use ex x x x Physical Regs op p1 ld p add sub p PR1 P7 P0 P6 CS152 Spring 08 LPRd P8 P7 P5 PRd P0 P1 P3 10 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P0 P7 P1 P2 P5 P3 P6 x x x x P0 P1 P2 P3 P4 P5 P6 P7 P8 R6 R7 R3 R1 Free List P0 P1 P3 P2 P4 p p p p ld r1 0 r3 add r3 r1 4 sub r6 r7 r6 add r3 r3 r6 ld r6 0 r1 Pn ROB use ex Physical Regs op p1 ld p add sub p add PR1 P7 P0 P6 P1 p2 PR2 p P5 P3 4 1 2008 Rd LPRd r1 r3 r6 r3 P8 P7 P5 P1 PRd P0 P1 P3 P2 11 CS152 Spring 08 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P0 P7 P1 P2 P5 P3 P4 P6 4 1 2008 P0 P1 P2 P3 P4 P5 P6 P7 P8 R6 R7 R3 R1 p p p p p2 PR2 p P5 P3 Rd r1 r3 r6 r3 r6 Free List P0 P1 P3 P2 P4 ld r1 0 r3 add r3 r1 4 sub r6 r7 r6 add r3 r3 r6 ld r6 0 r1 Pn ROB use ex x x x x x Physical Regs op p1 ld p add sub p add ld PR1 P7 P0 P6 P1 P0 CS152 Spring 08 LPRd P8 P7 P5 P1 P3 PRd P0 P1 P3 P2 P4 12 Physical Register Management R0 R1 R2 R3 R4 R5 R6 R7 Rename Table P8 P0 P7 P1 P2 P5 P3 P4 P6 x x x x x x P0 P1 P2 P3 P4 P5 P6 P7 P8 R1 R6 R7 R3 R1 Free List P0 P1 P3 P2 P4 p ld r1 0 r3 add r3 r1 4 sub r6 r7 r6 add r3 r3 r6 ld r6 0 r1 P8 p p p p Pn ROB use ex …
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