February 7, 2011 CS152, Spring 2011 CS 152 Computer Architecture and Engineering Lecture 6 - Memory Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste!http://inst.eecs.berkeley.edu/~cs152!February 7, 2011 CS152, Spring 2011 2 Last time in Lecture 5 • Control hazards (branches, interrupts) are most difficult to handle as they change which instruction should be executed next • Speculation commonly used to reduce effect of control hazards (predict sequential fetch, predict no exceptions) • Branch delay slots make control hazard visible to software • Precise exceptions: stop cleanly on one instruction, all previous instructions completed, no following instructions have changed architectural state • To implement precise exceptions in pipeline, shift faulting instructions down pipeline to “commit” point, where exceptions are handled in program orderFebruary 7, 2011 CS152, Spring 2011 Early Read-Only Memory Technologies 3 Punched cards, From early 1700s through Jaquard Loom, Babbage, and then IBM Punched paper tape, instruction stream in Harvard Mk 1 IBM Card Capacitor ROS IBM Balanced Capacitor ROS Diode Matrix, EDSAC-2 µcode storeFebruary 7, 2011 CS152, Spring 2011 Early Read/Write Main Memory Technologies 4 Williams Tube, Manchester Mark 1, 1947 Babbage, 1800s: Digits stored on mechanical wheels Mercury Delay Line, Univac 1, 1951 Also, regenerative capacitor memory on Atanasoff-Berry computer, and rotating magnetic drum memory on IBM 650February 7, 2011 CS152, Spring 2011 5 Core Memory • Core memory was first large scale reliable main memory – invented by Forrester in late 40s/early 50s at MIT for Whirlwind project • Bits stored as magnetization polarity on small ferrite cores threaded onto two-dimensional grid of wires • Coincident current pulses on X and Y wires would write cell and also sense original state (destructive reads) DEC PDP-8/E Board, 4K words x 12 bits, (1968) • Robust, non-volatile storage • Used on space shuttle computers until recently • Cores threaded onto wires by hand (25 billion a year at peak production) • Core access time ~ 1µsFebruary 7, 2011 CS152, Spring 2011 6 Semiconductor Memory • Semiconductor memory began to be competitive in early 1970s – Intel formed to exploit market for semiconductor memory – Early semiconductor memory was Static RAM (SRAM). SRAM cell internals similar to a latch (cross-coupled inverters). • First commercial Dynamic RAM (DRAM) was Intel 1103 – 1Kbit of storage on single chip – charge on a capacitor used to hold value • Semiconductor memory quickly replaced core in ‘70sFebruary 7, 2011 CS152, Spring 2011 7 One Transistor Dynamic RAM [Dennard, IBM] TiN top electrode (VREF) Ta2O5 dielectric W bottom electrode poly word line access transistor 1-T DRAM Cell word bit access transistor Storage capacitor (FET gate, trench, stack) VREFFebruary 7, 2011 CS152, Spring 2011 Modern DRAM Structure 8 [Samsung, sub-70nm DRAM, 2004]February 7, 2011 CS152, Spring 2011 9 DRAM Architecture Row Address Decoder Col. 1 Col. 2M Row 1 Row 2N Column Decoder & Sense Amplifiers M N N+M bit lines word lines Memory cell (one bit) D Data • Bits stored in 2-dimensional arrays on chip • Modern chips have around 4-8 logical banks on each chip – each logical bank physically implemented as many smaller arraysFebruary 7, 2011 CS152, Spring 2011 10 DRAM Packaging (Laptops/Desktops/Servers) • DIMM (Dual Inline Memory Module) contains multiple chips with clock/control/address signals connected in parallel (sometimes need buffers to drive signals to all chips) • Data pins work together to return wide word (e.g., 64-bit data bus using 16x4-bit parts) Address lines multiplexed row/column address Clock and control signals Data bus (4b,8b,16b,32b) DRAM chip ~12 ~7February 7, 2011 CS152, Spring 2011 DRAM Packaging, Mobile Devices 11 [ Apple A4 package cross-section, iFixit 2010 ] Two stacked DRAM die Processor plus logic die [ Apple A4 package on circuit board]February 7, 2011 CS152, Spring 2011 12 DRAM Operation Three steps in read/write access to a given bank • Row access (RAS) – decode row address, enable addressed row (often multiple Kb in row) – bitlines share charge with storage cell – small change in voltage detected by sense amplifiers which latch whole row of bits – sense amplifiers drive bitlines full rail to recharge storage cells • Column access (CAS) – decode column address to select small number of sense amplifier latches (4, 8, 16, or 32 bits depending on DRAM package) – on read, send latched bits out to chip pins – on write, change sense amplifier latches which then charge storage cells to required value – can perform multiple column accesses on same row without another row access (burst mode) • Precharge – charges bit lines to known value, required before next row access Each step has a latency of around 15-20ns in modern DRAMs Various DRAM standards (DDR, RDRAM) have different ways of encoding the signals for transmission to the DRAM, but all share same core architectureFebruary 7, 2011 CS152, Spring 2011 13 Double-Data Rate (DDR2) DRAM [ Micron, 256Mb DDR2 SDRAM datasheet ] Row Column Precharge Row’ Data 200MHz Clock 400Mb/s Data RateFebruary 7, 2011 CS152, Spring 2011 14 CPU-Memory Bottleneck Memory CPU Performance of high-speed computers is usually limited by memory bandwidth & latency • Latency (time for a single access) Memory access time >> Processor cycle time • Bandwidth (number of accesses per unit time) if fraction m of instructions access memory, ⇒1+m memory references / instruction ⇒ CPI = 1 requires 1+m memory refs / cycle (assuming MIPS RISC ISA)February 7, 2011 CS152, Spring 2011 Processor-DRAM Gap (latency) 15 Time µProc 60%/year DRAM 7%/year 1 10 100 1000 1980 1981 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 DRAM CPU 1982 Processor-Memory Performance Gap: (growing 50%/yr) Performance Four-issue 3GHz superscalar accessing 100ns DRAM could execute 1,200 instructions during time for one memory access!February 7, 2011 CS152, Spring 2011 Physical Size Affects Latency 16 Small Memory CPU Big Memory CPU • Signals have further to travel • Fan out to more locationsFebruary 7, 2011
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