Recap A Single Cycle Datapath CS 152 Computer Architecture and Engineering Lecture 8 Rs Rt Rd and Imed16 hardwired into datapath from Fetch Unit We have everything except control signals underline Instruction 31 0 Rt Rt Equal ALUctr 5 16 Rd Imm16 MemtoReg 0 32 Mux ALU Extender imm16 Rs MemWr Mux 32 Clk lecture slides http inst eecs berkeley edu cs152 5 0 15 Rs 5 busA Rw Ra Rb 32 32 32 bit Registers busB 0 32 busW John Kubiatowicz www cs berkeley edu kubitron Clk 1 Mux 0 RegWr February 23 2004 Rt 11 15 Rd RegDst 21 25 Single Cycle Con t Designing a Multicycle Processor Instruction Fetch Unit 16 20 nPC sel 32 1 WrEn Adr 1 Data In 32 32 Data Memory Clk ALUSrc Recap The Single Cycle Datapath during Add Recap Flexible Instruction Fetch 31 Branch nPC sel Br 16 rt 11 6 rd 0 shamt funct Instruction 31 0 What is encoding of nPC sel nPC MUX sel Direct MUX select Branch not branch Rs Adder 16 00 Rs Rd Imm16 MemtoReg 0 busA Rw Ra Rb 32 32 32 bit Registers busB 0 32 imm16 1 Rt Equal MemWr 0 1 32 0 32 32 WrEn Adr Data In 32 Clk Mux MUX 0 0 1 ALUctr Add Rt 5 Mux PC Mux Equal x 0 1 32 Clk 5 ALU busW 5 Extender Adder nPC sel 0 1 1 Clk 1 Mux 0 RegWr 1 Let s choose second option 4 Rt 0 15 Equal RegDst 1 11 15 Rd Adr Instruction Fetch Unit 16 20 nPC sel nPC sel 4 Instruction 31 0 21 25 Inst Memory imm16 21 rs R rd R rs R rt PC PC 4 2 23 04 26 op if Equal 1 then PC PC 4 SignExt imm16 4 else PC PC 4 Other nPC sel 4 0 CS152 Kubiatowicz Lec8 2 ExtOp UCB Spring 2004 2 23 04 1 Data Memory ALUSrc 0 Clk UCB Spring 2004 CS152 Kubiatowicz Lec8 3 2 23 04 ExtOp x UCB Spring 2004 CS152 Kubiatowicz Lec8 4 Recap The Single Cycle Datapath during Or Immediate 31 26 21 op 16 rs Recap The Single Cycle Datapath during Load 0 rt 31 26 immediate 21 op R rt R rs or ZeroExt Imm16 16 rs 0 rt immediate R rt Data Memory R rs SignExt imm16 Instruction 31 0 0 Data In 32 32 32 Clk 1 Data Memory Clk imm16 16 ExtOp 0 26 CS152 Kubiatowicz Lec8 5 UCB Spring 2004 21 op 16 rs 31 26 immediate Data Memory Clk CS152 Kubiatowicz Lec8 6 16 rs 0 rt immediate if R rs R rt 0 then Zero 1 else Zero 0 0 Clk 1 Data Memory imm16 16 ALUSrc 1 2 23 04 ExtOp 1 UCB Spring 2004 Rs Rd Imm16 MemtoReg x Equal MemWr 0 1 32 0 32 32 WrEn Adr Data In 32 Clk Mux 32 busA Rw Ra Rb 32 32 32 bit Registers busB 0 32 Extender Data In 32 Rt ALUctr Sub Mux 32 WrEn Adr 32 Clk Mux 32 Rt 5 ALU busW 5 0 15 MemWr 1 Rs 5 11 15 Equal Clk 1 Mux 0 RegWr 0 MemtoReg x Rt 16 20 Imm16 Rd RegDst x Instruction Fetch Unit 21 25 Rd Instruction 31 0 nPC sel Br 0 15 Rs 11 15 Rt ALU Extender 16 1 32 UCB Spring 2004 21 op 16 20 busA Rw Ra Rb 32 32 32 bit Registers busB 0 32 imm16 21 25 ALUctr Add Rt 5 Mux 32 Clk Rs 5 Instruction Fetch Unit Clk 1 Mux 0 RegWr 0 5 busW Rt 1 WrEn Adr Instruction 31 0 Rd 0 Recap The Single Cycle Datapath during Branch Data Memory R rs SignExt imm16 R rt RegDst x Imm16 MemtoReg 1 32 Data In 32 32 ExtOp 1 2 23 04 0 rt nPC sel 4 Rd ALUSrc 1 Recap The Single Cycle Datapath during Store 31 Rs Equal MemWr 0 1 ALUSrc 1 2 23 04 Rt Mux 32 ALUctr Add Rt 5 Mux 32 Rs 5 busA Rw Ra Rb 32 32 32 bit Registers busB 0 32 MemWr 0 WrEn Adr 1 RegWr 1 5 Extender 16 Imm16 MemtoReg 0 ALU ALU Extender imm16 Rd busW Mux 32 Clk Equal Rs Mux busA Rw Ra Rb 32 32 32 bit Registers busB 0 32 busW Rt ALUctr Or Clk 1 Mux 0 0 15 Rt 5 Rt 11 15 Rs 5 Rd RegDst 0 Instruction Fetch Unit 16 20 RegWr 1 5 nPC sel 4 21 25 1 Mux 0 0 15 Clk Instruction 31 0 11 15 Rt 16 20 Rd RegDst 0 Instruction Fetch Unit 21 25 nPC sel 4 1 Data Memory ALUSrc 0 CS152 Kubiatowicz Lec8 7 2 23 04 ExtOp x UCB Spring 2004 CS152 Kubiatowicz Lec8 8 Recap A Summary of Control Signals inst Register Transfer ADD R rd R rs R rt Step 5 Assemble Control logic Instruction 31 0 Op Fun ORi R rt R rs zero ext Imm16 Rt Rs Imm16 PC PC 4 Decoder ALUsrc Im Extop Z ALUctr or RegDst rt RegWr nPC sel 4 LOAD Rd 0 15 Adr ALUsrc RegB ALUctr sub RegDst rd RegWr nPC sel 4 11 15 PC PC 4 16 20 R rd R rs R rt 21 25 Inst Memory ALUsrc RegB ALUctr add RegDst rd RegWr nPC sel 4 SUB 21 25 PC PC 4 R rt MEM R rs sign ext Imm16 PC PC 4 ALUsrc Im Extop Sn ALUctr add MemtoReg RegDst rt RegWr nPC sel 4 nPC sel RegWr RegDst ExtOp ALUSrc ALUctr MemWr MemtoReg STORE MEM R rs sign ext Imm16 R rs BEQ if R rs R rt then PC PC sign ext Imm16 00 else PC PC 4 Equal PC PC 4 ALUsrc Im Extop Sn ALUctr add MemWr nPC sel 4 DATA PATH nPC sel Br ALUctr sub 2 23 04 CS152 Kubiatowicz Lec8 9 UCB Spring 2004 A Summary of the Control Signals 2 23 04 The Concept of Local Decoding func 10 0000 10 0010 See Appendix A op We Don t Care op 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100 00 0000 ori lw sw beq sub ori lw sw beq RegDst 1 0 0 x x RegDst 1 1 0 0 x x ALUSrc 0 1 1 1 0 ALUSrc 0 0 1 1 1 0 MemtoReg 0 0 1 x x MemtoReg 0 0 0 1 x x RegWrite 1 1 1 0 0 RegWrite 1 1 1 1 0 0 MemWrite 0 0 0 1 0 MemWrite 0 0 0 0 1 0 Branch 0 0 0 0 1 nPCsel 0 0 0 0 0 1 ExtOp x 0 1 1 x ExtOp x x 0 1 1 x ALUop N 0 R type Or Add Add Subtract Add Subtract Or Add Add Subtract 31 26 21 16 op rs rt I type op rs rt J type op rd 6 shamt func 0 funct op add sub 6 immediate target address UCB Spring 2004 Main Control 6 …
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