CS 152Computer Architecture and EngineeringLecture 8Single-Cycle (Con’t)Designing a Multicycle ProcessorFebruary 23, 2004John Kubiatowicz (www.cs.berkeley.edu/~kubitron)lecture slides: http://inst.eecs.berkeley.edu/~cs152/2/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.2Recap: A Single Cycle Datapath° Rs, Rt, Rd and Imed16 hardwired into datapath from Fetch Unit° We have everything except control signals (underline)32ALUctrClkbusWRegWr3232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDstExtenderMuxMux3216imm16ALUSrcExtOpMuxMemtoRegClkData InWrEn32AdrDataMemory32MemWrALUInstructionFetch UnitClkEqualInstruction<31:0>010101<21:25><16:20><11:15><0:15>Imm16RdRsRtnPC_sel2/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.3Recap: Flexible Instruction Fetch° Branch (nPC_sel = “Br”):• if (Equal == 1) then PC = PC + 4 + SignExt[imm16]*4 ; else PC = PC + 4° Other (nPC_sel = “+4”): • PC=PC+4° What is encoding of nPC_sel?• Direct MUX select?• Branch / not branch° Let’s choose second optionnPC_sel Equal MUX0x 010 011 1AdrInstMemoryAdderAdderPCClk00Mux4nPC_selimm16Instruction<31:0>01EqualnPC_MUX_sel2/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.4Recap: The Single Cycle Datapath during Add32ALUctr = AddClkbusWRegWr = 13232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDst = 1ExtenderMuxMux3216imm16ALUSrc = 0ExtOp = xMuxMemtoReg = 0ClkData InWrEn32AdrDataMemory32MemWr = 0ALUInstructionFetch UnitClkEqualInstruction<31:0>° R[rd] <- R[rs] + R[rt]010101<21:25><16:20><11:15><0:15>Imm16RdRsRtop rs rt rd shamt funct061116212631nPC_sel= +42/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.5Recap: The Single Cycle Datapath during Or Immediate32ALUctr = OrClkbusWRegWr = 13232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDst = 0ExtenderMuxMux3216imm16ALUSrc = 1ExtOp = 0MuxMemtoReg = 0ClkData InWrEn32AdrDataMemory32MemWr = 0ALUInstructionFetch UnitClkEqualInstruction<31:0>° R[rt] <- R[rs] or ZeroExt[Imm16]010101<21:25><16:20><11:15><0:15>Imm16RdRsRtop rs rt immediate016212631nPC_sel= +42/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.6Recap: The Single Cycle Datapath during Load32ALUctr= AddClkbusWRegWr = 13232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDst = 0ExtenderMuxMux3216imm16ALUSrc = 1ExtOp = 1MuxMemtoReg = 1ClkData InWrEn32AdrDataMemory32MemWr = 0ALUInstructionFetch UnitClkEqualInstruction<31:0>010101<21:25><16:20><11:15><0:15>Imm16RdRsRt° R[rt] <- Data Memory {R[rs] + SignExt[imm16]}op rs rt immediate016212631nPC_sel= +42/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.7Recap: The Single Cycle Datapath during Store32ALUctr= AddClkbusWRegWr = 03232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDst = xExtenderMuxMux3216imm16ALUSrc = 1ExtOp = 1MuxMemtoReg = xClkData InWrEn32AdrDataMemory32MemWr = 1ALUInstructionFetch UnitClkEqualInstruction<31:0>010101<21:25><16:20><11:15><0:15>Imm16RdRsRt° Data Memory {R[rs] + SignExt[imm16]} <- R[rt]op rs rt immediate016212631nPC_sel= +42/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.8Recap: The Single Cycle Datapath during Branch32ALUctr =SubClkbusWRegWr = 03232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDst = xExtenderMuxMux3216imm16ALUSrc = 0ExtOp = xMuxMemtoReg = xClkData InWrEn32AdrDataMemory32MemWr = 0ALUInstructionFetch UnitClkEqualInstruction<31:0>010101<21:25><16:20><11:15><0:15>Imm16RdRsRt° if (R[rs] - R[rt] == 0) then Zero <- 1 ; else Zero <- 0op rs rt immediate016212631nPC_sel= “Br”2/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.9Recap: A Summary of Control Signalsinst Register TransferADD R[rd] <– R[rs] + R[rt]; PC <– PC + 4ALUsrc = RegB, ALUctr = “add”, RegDst = rd, RegWr, nPC_sel = “+4”SUB R[rd] <– R[rs] – R[rt]; PC <– PC + 4ALUsrc = RegB, ALUctr = “sub”, RegDst = rd, RegWr, nPC_sel = “+4”ORi R[rt] <– R[rs] + zero_ext(Imm16); PC <– PC + 4ALUsrc = Im, Extop = “Z”, ALUctr = “or”, RegDst = rt, RegWr, nPC_sel = “+4”LOAD R[rt] <– MEM[ R[rs] + sign_ext(Imm16)]; PC <– PC + 4ALUsrc = Im, Extop = “Sn”, ALUctr = “add”,MemtoReg, RegDst = rt, RegWr, nPC_sel = “+4”STORE MEM[ R[rs] + sign_ext(Imm16)] <– R[rs]; PC <– PC + 4ALUsrc = Im, Extop = “Sn”, ALUctr = “add”, MemWr, nPC_sel = “+4”BEQ if ( R[rs] == R[rt] ) then PC <– PC + sign_ext(Imm16)] || 00 else PC <– PC + 4nPC_sel = “Br”, ALUctr = “sub”2/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.10Step 5: Assemble Control logicALUctrRegDstALUSrcExtOpMemtoRegMemWrEqualInstruction<31:0><21:25><16:20><11:15><0:15>Imm16RdRsRtnPC_selAdrInstMemoryDATA PATHDecoderOp<21:25>FunRegWr2/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.11A Summary of the Control Signalsadd sub ori lw sw beqRegDstALUSrcMemtoRegRegWriteMemWritenPCselExtOpALUctr<2:0>100100xAdd100100xSubtract0101000Or0111001Addx1x0101Addx0x001xSubtractop target addressop rs rt rd shamt funct061116212631op rs rtimmediateR-typeI-typeJ-typeadd, subori, lw, sw, beqjumpfuncop 00 0000 00 0000 00 1101 10 0011 10 1011 00 0100Appendix A10 0000See 10 0010We Don’t Care :-)2/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.12The Concept of Local DecodingMainControlop6ALUControl(Local)funcN6ALUopALUctr3ALUR-type ori lw sw beqRegDstALUSrcMemtoRegRegWriteMemWriteBranchExtOpALUop<N:0>100100x“R-type”0101000Or0111001Addx1x0101Addx0x001xSubtractop 00 0000 00 1101 10 0011 10 1011 00 01002/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.13The Encoding of ALUop° ALUop has to be 2 bits wide to represent:• (1) “R-type” instructions• “I-type” instructions that require the ALU to perform:- (2) Or, (3) Add, and (4) SubtractMainControlop6ALUControl(Local)funcN6ALUopALUctr3R-type ori lw sw beqALUop (Symbolic) “R-type” Or Add AddSubtractALUop<2:0> 1 00 0 10 0 00 0 000 012/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.14The Decoding of the “func” FieldMainControlop6ALUControl(Local)funcN6ALUopALUctr3op rs rt rd shamt funct061116212631R-typefunct<5:0> Instruction Operation10 000010 001010 010010 010110 1010addsubtractandorset-on-less-thanALUctr<2:0> ALU Operation000001010110111AndOrAddSubtractSet-on-less-thanP. 286 text:ALUctrALUR-type ori lw sw beqALUop (Symbolic) “R-type” Or Add AddSubtractALUop<2:0> 1 00 0 10 0 00 0 000 012/23/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec8.15The Truth Table for ALUctrR-type ori lw sw beqALUop(Symbolic)“R-type” Or Add AddSubtractALUop<2:0> 1 00 0 10 0 00 0 000 01ALUop funcbit<2>
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