1CS 152 L12 RAW Hazards, Interrrupts(1) Fall 2004 © UC RegentsCS152 – Computer Architecture andEngineeringLecture 12 – Pipeline Wrap up: Control Hazards, RAW/WAR/WAW2004-10-07John Lazzaro(www.cs.berkeley.edu/~lazzaro)Dave Patterson (www.cs.berkeley.edu/~patterson)www-inst.eecs.berkeley.edu/~cs152/CS 152 L12 RAW Hazards, Interrrupts (2) Fall 2004 © UC RegentsPipelining Review• What makes it easy– all instructions are the same length– just a few instruction formats– memory operands appear only in loads and stores• Hazards limit performance– Structural: need more HW resources– Data: need forwarding, compiler scheduling• Data hazards must be handled carefully• MIPS I instruction set architecture made pipeline visible (delayed branch, delayed load)CS 152 L12 RAW Hazards, Interrrupts (3) Fall 2004 © UC RegentsOutline• Pipelined Control• Control Hazards • RAW, WAR, WAW• Brainstorm on pipeline bugsCS 152 L12 RAW Hazards, Interrrupts (4) Fall 2004 © UC RegentsMIPS Pipeline Data / Control Paths A (fast)ReadAddressInstructionMemoryAddPC401Write DataRead Addr 1Read Addr 2Write AddrRegisterFileReadData 1ReadData 216 32ALU10Shiftleft 2AddDataMemoryAddressWrite DataReadData10IF/IDSignExtendID/EXEX/MEMMEM/WBControl01ALUcntrlRegWriteMemWrite MemReadMemtoRegRegDstALUOpALUSrcBranchPCSrcEXMEMWBCS 152 L12 RAW Hazards, Interrrupts (5) Fall 2004 © UC RegentsMIPS Pipeline Data / Control Paths (debug)ReadAddressInstructionMemoryAddPC401Write DataRead Addr 1Read Addr 2Write AddrRegisterFileReadData 1ReadData 216 32ALU10Shiftleft 2AddDataMemoryAddressWrite DataReadData10IF/IDSignExtendID/EX EX/MEMMEM/WB01ALUcntrlRegWriteMemWrite MemReadMemtoRegRegDstALUOpALUSrcBranchPCSrcControlInstrControlInstrControlInstrEX MEM WBCS 152 L12 RAW Hazards, Interrrupts (6) Fall 2004 © UC RegentsMIPS Pipeline Control (pipelined debug)ReadAddressInstructionMemoryAddPC401Write DataRead Addr 1Read Addr 2Write AddrRegisterFileReadData 1ReadData 216 32ALU10Shiftleft 2AddDataMemoryAddressWrite DataReadData10IF/IDSignExtendID/EX EX/MEMMEM/WB01ALUcntrlRegWriteMemWrite MemReadMemtoRegRegDstALUOpALUSrcBranchPCSrcMEMWBInstrControlEXInstrControlInstrControl2CS 152 L12 RAW Hazards, Interrrupts (7) Fall 2004 © UC RegentsControl Hazards• When the flow of instruction addresses is not what the pipeline expects; incurred by change of flow instructions– Conditional branches (beq, bne)– Unconditional branches (j)• Possible solutions– Stall– Move decision point earlier in the pipeline– Predict– Delay decision (requires compiler support)CS 152 L12 RAW Hazards, Interrrupts (8) Fall 2004 © UC RegentsDatapath Branch and Jump HardwareID/EXReadAddressInstructionMemoryAddPC4Write DataRead Addr 1Read Addr 2Write AddrRegisterFileReadData 1ReadData 216 32ALU10DataMemoryAddressWrite DataReadData10IF/IDSignExtendEX/MEMMEM/WBControl01ALUcntrlForwardUnitCS 152 L12 RAW Hazards, Interrrupts (9) Fall 2004 © UC RegentsDatapath Branch and Jump HardwareID/EXReadAddressInstructionMemoryAddPC4Write DataRead Addr 1Read Addr 2Write AddrRegisterFileReadData 1ReadData 216 32ALU10DataMemoryAddressWrite DataReadData10IF/IDSignExtendEX/MEMMEM/WBControl01ALUcntrlForwardUnit01BranchPCSrcShiftleft 2Add01Shiftleft 2JumpPC+4[31-28]CS 152 L12 RAW Hazards, Interrrupts (10) Fall 2004 © UC RegentsAdministrivia• Finish Lab 3; meet with TA Friday• Midterm Tue Oct 12 5:30 - 8:30 in 101 Morgan– Northwest corner of campus, near Arch and Hearst– Midterm review Sunday Oct 10, 7 PM, 306 Soda– Bring 1 page, handwritten notes, both sides– Nothing electronic: no calculators, cell phones, pagers, …– Meet at LaVal’s Northside afterwards for PizzaCS 152 L12 RAW Hazards, Interrrupts (11) Fall 2004 © UC RegentsstallJumps Incur One StallInstr.OrderjlwandALUIMRegDM RegALUIMRegDM RegALUIMRegDM Reg• Fortunately, jumps are very infrequent –only 2% of the SPECint instruction mix• Jumps not decoded until ID, so one stall is neededCS 152 L12 RAW Hazards, Interrrupts (12) Fall 2004 © UC RegentsstallstallstallReview: Branches Incur Three StallsInstr.OrderbeqALUIM Reg DM ReglwALUIMRegDM RegALUandIMRegDMCan fix branch hazard by waiting –stall – but affects throughput3CS 152 L12 RAW Hazards, Interrrupts (13) Fall 2004 © UC RegentsMoving Branch Decisions Earlier in Pipe• Move the branch decision hardware back to the EX stage– Reduces the number of stall cycles to two– Adds an and gate and a 2x1 mux to the EX timing path• Add hardware to compute the branch target address and evaluate the branch decision to the ID stage– Reduces the number of stall cycles to one (like with jumps)– Computing branch target address can be done in parallel with RegFile read (done for all instructions – only used when needed)– Comparing the registers can’t be done until after RegFile read, so comparing and updating the PC adds a comparator, an and gate, and a 3x1 mux to the ID timing path– Need forwarding hardware in ID stage• For longer pipelines, decision points are later in the pipeline, incurring more stalls, so we need a better solutionCS 152 L12 RAW Hazards, Interrrupts (14) Fall 2004 © UC RegentsEarly Branch Forwarding Issues• Bypass of source operands from the EX/MEMif (IDcontrol.Branchand (EX/MEM.RegisterRd != 0)and (EX/MEM.RegisterRd == IF/ID.RegisterRs))ForwardC = 1if (IDcontrol.Branchand (EX/MEM.RegisterRd != 0)and (EX/MEM.RegisterRd == IF/ID.RegisterRt))ForwardD = 1Forwards the result from the second previous instr. to either input of the Compare• MEM/WB dependency also needs to be forwarded• If the instruction 2 before the branch is a load, then a stall will be required since the MEM stage memory access is occurring at the same time as the ID stage branch compare operationCS 152 L12 RAW Hazards, Interrrupts (15) Fall 2004 © UC RegentsBranch Prediction• Resolve branch hazards by assuming a given outcome and proceeding without waiting to see the actual branch outcome1. Predict not taken – always predict branches will not be taken, continue to fetch from the sequential instruction stream, only when branch is taken does the pipeline stall– If taken, flush instructions in the pipeline after the branch• in IF, ID, and EX if branch logic in MEM – three stalls• in IF if branch logic in ID – one stall– ensure that those flushed instructions haven’t changed machine state– automatic in the MIPS pipeline since machine state changing operations are at the tail end of the pipeline (MemWrite or
View Full Document
Unlocking...