Pipelining Review What makes it easy CS152 Computer Architecture and Engineering Lecture 12 Pipeline Wrap up Control Hazards RAW WAR WAW all instructions are the same length just a few instruction formats memory operands appear only in loads and stores Hazards limit performance Structural need more HW resources Data need forwarding compiler scheduling 2004 10 07 John Lazzaro Data hazards must be handled carefully MIPS I instruction set architecture made pipeline visible delayed branch delayed load www cs berkeley edu lazzaro Dave Patterson www cs berkeley edu patterson www inst eecs berkeley edu cs152 CS 152 L12 RAW Hazards Interrrupts 1 Fall 2004 UC Regents CS 152 L12 RAW Hazards Interrrupts 2 Outline MIPS Pipeline Data Control Paths A fast 1 Pipelined Control Control Hazards RAW WAR WAW Brainstorm on pipeline bugs PCSrc ID EX 0 EX Control IF ID EX MEM MEM Add RegWrite 4 Shift left 2 Data Memory Register Read Read Addr 2Data 1 Read Address ALUSrc File Write Addr Write Data 16 Read Data 2 32 Address ALU 0 ALU cntrl WB MemtoReg Read Data 1 0 Write Data 1 Sign Extend MEM WB Branch Add Read Addr 1 Instruction Memory PC Fall 2004 UC Regents MemWrite MemRead ALUOp 0 1 RegDst Fall 2004 UC Regents CS 152 L12 RAW Hazards Interrrupts 4 MEM WB EX Control Add RegWrite 4 PC Instruction Memory Read Address Shift left 2 Add Read Addr 1 Register Read Read Addr 2Data 1 File Write Addr Write Data 16 Sign Extend Control Read Data 2 0 1 32 ALU WB Control EX IF ID MEM Control Address Read Data 1 0 Read Address Control File Write Addr Write Data 16 Sign Extend Read Data 2 0 1 32 0 1 RegDst RegDst CS 152 L12 RAW Hazards Interrrupts 6 Branch Data Memory ALUSrc 1 Fall 2004 UC Regents Add Read Addr 1 MemWrite MemRead ALUOp Shift left 2 Register Read Read Addr 2Data 1 MEM WB WB Control RegWrite Instruction Memory MemtoReg PCSrc EX MEM Add 4 Write Data ALU cntrl ID EX 0 Branch Data Memory ALUSrc 0 CS 152 L12 RAW Hazards Interrrupts 5 MEM Instr Instr Instr IF ID 1 PCSrc EX MEM Instr ID EX 0 PC 1 MIPS Pipeline Control pipelined debug Instr MIPS Pipeline Data Control Paths debug Fall 2004 UC Regents Instr CS 152 L12 RAW Hazards Interrrupts 3 ALU Address Read Data 1 0 Write Data ALU cntrl MemtoReg MemWrite MemRead ALUOp Fall 2004 UC Regents 1 Control Hazards Datapath Branch and Jump Hardware When the flow of instruction addresses is not what the pipeline expects incurred by change of flow instructions ID EX IF ID Conditional branches beq bne Unconditional branches j EX MEM Control Add MEM WB 4 PC Instruction Memory Possible solutions Read Address Read Addr 1 File Write Addr Write Data Stall Move decision point earlier in the pipeline Predict Delay decision requires compiler support CS 152 L12 RAW Hazards Interrrupts 7 Data Memory Register Read Read Addr 2Data 1 16 Sign Extend Read Data 2 ALU 1 Read Data Address 1 0 Write Data 0 ALU cntrl 32 0 1 Forward Unit Fall 2004 UC Regents CS 152 L12 RAW Hazards Interrrupts 8 Fall 2004 UC Regents Administrivia Datapath Branch and Jump Hardware Jump 1 PCSrc 1 0 IF ID PC 4 31 28 4 PC Read Address EX MEM Control Add Instruction Memory ID EX Shift left 2 0 Add Shift left 2 Read Addr 1 File Write Data 16 Sign Extend Northwest corner of campus near Arch and Hearst Midterm review Sunday Oct 10 7 PM 306 Soda Bring 1 page handwritten notes both sides Nothing electronic no calculators cell phones pagers Meet at LaVal s Northside afterwards for Pizza Data Memory Register Read Read Addr 2Data 1 Write Addr MEM WB Branch Finish Lab 3 meet with TA Friday Midterm Tue Oct 12 5 30 8 30 in 101 Morgan Read Data 2 Address ALU 1 Read Data 0 1 0 Write Data ALU cntrl 32 0 1 Forward Unit CS 152 L12 RAW Hazards Interrrupts 9 Fall 2004 UC Regents Jumps Incur One Stall CS 152 L12 RAW Hazards Interrrupts 10 Fall 2004 UC Regents Review Branches Incur Three Stalls Jumps not decoded until ID so one stall is needed Reg stall DM IM Reg Reg DM Reg CS 152 L12 RAW Hazards Interrrupts 11 Fall 2004 UC Regents O r d e r stall IM Reg DM Can fix branch hazard by waiting stall but affects throughput Reg stall stall lw and CS 152 L12 RAW Hazards Interrrupts 12 IM Reg IM Reg DM ALU Fortunately jumps are very infrequent only 2 of the SPECint instruction mix beq ALU and Reg ALU lw IM I n s t r ALU Reg DM ALU O r d e r j ALU I n s t r IM Reg DM Fall 2004 UC Regents 2 Early Branch Forwarding Issues Moving Branch Decisions Earlier in Pipe Move the branch decision hardware back to the EX stage Bypass of source operands from the EX MEM if IDcontrol Branch and EX MEM RegisterRd and EX MEM RegisterRd ForwardC 1 if IDcontrol Branch and EX MEM RegisterRd and EX MEM RegisterRd ForwardD 1 Reduces the number of stall cycles to two Adds an and gate and a 2x1 mux to the EX timing path Add hardware to compute the branch target address and evaluate the branch decision to the ID stage Reduces the number of stall cycles to one like with jumps Computing branch target address can be done in parallel with RegFile read done for all instructions only used when needed Comparing the registers can t be done until after RegFile read so comparing and updating the PC adds a comparator an and gate and a 3x1 mux to the ID timing path Need forwarding hardware in ID stage 0 IF ID RegisterRt Fall 2004 UC Regents CS 152 L12 RAW Hazards Interrrupts 14 Fall 2004 UC Regents Flushing with Misprediction Not Taken Branch Prediction If taken flush instructions in the pipeline after the branch in IF ID and EX if branch logic in MEM three stalls in IF if branch logic in ID one stall ensure that those flushed instructions haven t changed machine state automatic in the MIPS pipeline since machine state changing operations are at the tail end of the pipeline MemWrite or RegWrite restart the pipeline at the branch destination CS 152 L12 RAW Hazards Interrrupts 15 4 beq 1 2 2 I n s t r 8 sub 4 1 5 Fall 2004 UC Regents 16 and 6 1 7 20 or r8 1 9 Reg DM IM Reg IM Reg DM DM Reg To flush the IF stage instruction add a IF Flush control line that zeros the instruction field of the IF ID pipeline register transforming it into a noop CS 152 L12 RAW Hazards Interrrupts 16 Fall 2004 UC Regents Resolve branch hazards by statically assuming a given outcome and proceeding 2 Predict taken always predict branches will be taken Predict taken always incurs a stall if branch destination hardware has been moved to the ID stage Reg DM Reg …
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