1 CS152 – Computer Architecture and Engineering University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences Compiled: 2004-09-16 for CS152, Prof. Dave Patterson, John Lazzaro Sources: http://www.cs.berkeley.edu/~kubitron/courses/cs152-S04/handouts/homeworklab_2.html http://www-inst.eecs.berkeley.edu/~cs150/fa04/ - various material with permission Mini Lab 3: Downloading to the Calinx board Name: Date Login: Prelab Checkoff Section: Lab Checkoff Introduction: Mini Lab 3 is the final part of a 3 part mini-lab series designed to orient you with the concepts of our CAD tool flow as well as let you get hands-on experience with industrial strength CAD tools. We will be going over how to implement your design on a Field Programmable Gate Array (FPGA) based board. This lab is to be done individually and is due at the end of your section. You should be able to show us the steps you took, and explain what they mean. IMPORTANT: Please read the lab report (and examine the references) and answer the following questions before coming to lab. Prelab Questions: 1. What does FPGA stand for? What is the FPGA that you will use this semester (specific part)? What is a LUT (theoretically and physically)? How many logic functions can a LUT on our part realize? How many LUTs in a Slice on our part? What other two major elements are in a Slice for our part? What is a CLB and how many slices does it have for our part? How many CLBs does the FPGA we use have and therefore how many total LUTs?2 2. Give three advantages FPGAs have over ASICS. Give three weaknesses. 3. What is the synthesis tool we will be using? What is the product (result) of the synthesis tool fed a verilog description? Could different synthesis tools produce different results given the same input? 4. What is the program we use to download the design to the Xilinx chip? What type of cable is used for the programming? What is it programming physically? What interface does this cable use to program the device? Is this the only way to program the board? If not what is another way? Lab Questions: 1. How many slice Flip Flops does your design use? How many occupied Slices? How many 4-input LUTs? 2. What is the Minimum Period for the clock in your design? Therefore what is the maximum clock frequency?3 CS152 – Computer Architecture and Engineering University of California at Berkeley College of Engineering Department of Electrical Engineering and Computer Sciences Compiled: 2004-09-04 for CS152, Prof. Dave Patterson, John Lazzaro Sources: http://www.cs.berkeley.edu/~kubitron/courses/cs152-S04/handouts/homeworklab_2.html http://www-inst.eecs.berkeley.edu/~cs150/fa04/ - various material used with permission Mini Lab 3: Downloading to the Calinx board 1 REFERENCES ......................................................................................................................3 2 OVERVIEW...........................................................................................................................3 2.1 PLATFORM.........................................................................................................................4 2.2 SYNTHESIS.........................................................................................................................4 2.3 PLACEMENT, ROUTING.......................................................................................................4 2.4 PROGRAM HARDWARE.......................................................................................................4 2.5 VERIFICATION....................................................................................................................4 3 IMPLEMENTING YOUR MULTIPLIER DESIGN ...........................................................5 3.1 SYNTHESIS.........................................................................................................................6 3.2 PLACE AND ROUTE.............................................................................................................6 3.2.1 Alternative Method .....................................................................................................7 3.3 DOWNLOAD DESIGN TO THE BOARD...................................................................................7 3.4 TESTING THE MULTIPLIER..................................................................................................7 3.5 EXAMINING REPORTS.........................................................................................................8 1 References General Information • Calinx Board - http://calinx.eecs.berkeley.edu/ • Xilinx Virtex-E Data Sheet - http://inst.eecs.berkeley.edu/~cs152/handouts/virtexE-datasheet.pdf • CS150 FPGA Overview - http://www-inst.eecs.berkeley.edu/~cs150/fa04/Lecture/lec03.pdf • Xilinx Web Site – http://www.xilinx.com Computer Organization and Design: The HW/SW Interface (3rd Edition) • Appendix B77-78 on Field Programmable Devices (FPDs) • Appendix B77 on Field Programmable Gate Arrays (FPGAs) Synplify Manual - http://www-inst.eecs.berkeley.edu/~cs152/handouts/local_only/synplify_ref.pdf • Appendix H – Designing with Xilinx • Pages 8-7 to 8-9 on Verilog Synthesis Guidelines 2 Overview This section is meant to detail the process of actually creating and implementing your own hardware designs.4 2.1 Platform This semester you will be using the Xilinx based Calinx boards to realize your designs. This board has both the Xilinx FPGA as well as other peripherals such as an AC ‘97 Audio Codec, video encoder/decoder, ethernet ports, and other items such as LEDs and switches. The first stage of the process is design entry. You will create your designs in the Hardware Description Language (HDL) verilog (or verilog produced through schematic capture) and then use a set of CAD tools to transfer your design to this board. The next portion of the flow to the board encompasses a series of steps including synthesis, place and route, programming, and verification. The next sections give overviews into those areas. 2.2 Synthesis Once your design is entered, the next step in the implementation path is synthesis. In our case, the function of the synthesis program is to translate the Verilog description of the circuit into an equivalent circuit comprising a set of primitive circuit components that can be
View Full Document
Unlocking...