CS 152 Computer Architecture and Engineering Lecture 5 Pipelining II Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http www eecs berkeley edu krste http inst eecs berkeley edu cs152 February 2 2010 CS152 Spring 2010 Last time in Lecture 4 Pipelining increases clock frequency while growing CPI more slowly hence giving greater performance Time Instructions Cycles Time Program Program Instruction Cycle Increases because of pipeline bubbles Reduces because fewer logic gates on critical paths between flip flops Pipelining of instructions is complicated by HAZARDS Structural hazards two instructions want same hardware resource Data hazards earlier instruction produces value needed by later instruction Control hazards instruction changes control flow e g branches or exceptions Techniques to handle hazards Interlock hold newer instruction until older instructions drain out of pipeline and write back results Bypass transfer value from older instruction to newer instruction as soon as available somewhere in machine Speculate guess effect of earlier instruction February 2 2010 CS152 Spring 2010 2 Control Hazards What do we need to calculate next PC For Jumps Opcode offset and PC For Jump Register Opcode and Register value For Conditional Branches Opcode PC Register for condition and offset For all other instructions Opcode and PC have to know it s not one of above February 2 2010 CS152 Spring 2010 3 PC Calculation Bubbles assuming no branch delay slots for now time t0 t1 t2 t3 I1 r1 r0 10 IF1 ID1 EX1 MA1 I2 r3 r2 17 IF2 IF2 ID2 I3 IF3 I4 Resource Usage IF ID EX MA WB time t0 t1 t2 I1 nop I2 I1 nop I1 t3 t4 t5 WB1 EX2 MA2 IF3 ID3 IF4 t4 nop I3 I2 nop nop I2 I1 nop I1 t6 t5 t6 nop I4 I3 nop nop I3 I2 nop nop I2 CS152 Spring 2010 WB2 EX3 MA3 WB3 IF4 ID4 EX4 MA4 WB4 nop February 2 2010 t7 t7 I4 nop I4 I3 nop I4 nop I3 nop I4 pipeline bubble 4 Speculate next address is PC 4 PCSrc pc 4 jabs rind br stall Add nop 0x4 Add Jump PC 104 I1 I2 I3 I4 addr inst February 2 2010 M IR IR I1 IR Inst Memory 096 100 104 304 E I2 ADD J 304 ADD ADD kill A jump instruction kills not stalls the following instruction CS152 Spring 2010 How 5 Pipelining Jumps PCSrc pc 4 jabs rind br stall To kill a fetched instruction Insert a mux before IR Add nop 0x4 Add Jump 304 104 I1 I2 I3 I4 addr inst nop Inst Memory 096 100 104 304 February 2 2010 IR nop I2 ADD J 304 ADD ADD kill M IR IR II21 I1 Any interaction between stall and jump IRSrcD PC E IRSrcD Case opcodeD J JAL nop IM CS152 Spring 2010 6 Jump Pipeline Diagrams I1 I2 I3 I4 096 100 104 304 ADD J 304 ADD ADD Resource Usage IF ID EX MA WB time t0 t1 t2 IF1 ID1 EX1 IF2 ID2 IF3 time t0 t1 I1 I2 I1 t2 I3 I2 I1 t3 MA1 EX2 nop IF4 t4 WB1 MA2 nop ID4 t5 t3 I4 nop I2 I1 t4 I5 I4 nop I2 I1 t5 t6 CS152 Spring 2010 WB2 nop nop EX4 MA4 WB4 t6 t7 I5 I4 I5 nop I4 I5 I2 nop I4 nop February 2 2010 t7 I5 pipeline bubble 7 Pipelining Conditional Branches PCSrc pc 4 jabs rind br stall Add nop 0x4 Add E M IR IR I1 BEQZ zero IRSrcD PC 104 I1 I2 I3 I4 addr inst nop Inst Memory 096 100 104 304 February 2 2010 ADD BEQZ r1 200 ADD ADD A IR ALU Y I2 Branch condition is not known until the execute stage what action should be taken in the decode stage CS152 Spring 2010 8 Pipelining Conditional Branches PCSrc pc 4 jabs rind br stall Add E nop 0x4 Add M BEQZ IR IR I2 I1 zero IRSrcD PC 108 I1 I2 I3 I4 addr inst Inst Memory 096 100 104 304 February 2 2010 nop IR A ALU Y I3 If the branch is taken ADD kill the two following instructions BEQZ r1 200 the instruction at the decode stage ADD is not valid ADD stall signal is not valid CS152 Spring 2010 9 Pipelining Conditional Branches stall Add PCSrc pc 4 jabs rind br E IRSrcE nop 0x4 Add Jump M BEQZ IR IR I2 I1 zero PC PC 108 I1 I2 I3 I4 addr IRSrcD inst Inst Memory 096 100 104 304 February 2 2010 nop IR A ALU Y I3 If the branch is taken ADD kill the two following instructions BEQZ r1 200 the instruction at the decode stage ADD is not valid ADD stall signal is not valid CS152 Spring 2010 10 New Stall Signal stall rsD wsE weE rsD wsM weM rsD wsW weW re1D rtD wsE weE rtD wsM weM rtD wsW weW re2D opcodeE BEQZ z opcodeE BNEZ z Don t stall if the branch is taken Why Instruction at the decode stage is invalid February 2 2010 CS152 Spring 2010 11 Control Equations for PC and IR Muxes PCSrc Case opcodeE BEQZ z BNEZ z br Case opcodeD J JAL JR JALR jabs rind pc 4 IRSrcD Case opcodeE BEQZ z BNEZ z nop Case opcodeD J JAL JR JALR nop IM Give priority to the older instruction i e execute stage instruction over decode stage instruction IRSrcE Case opcodeE BEQZ z BNEZ z nop stall nop stall IRD February 2 2010 CS152 Spring 2010 12 Branch Pipeline Diagrams resolved in execute stage I1 I2 I3 I4 I5 time t0 t1 t2 096 ADD IF1 ID1 EX1 100 BEQZ 200 IF2 ID2 104 ADD IF3 108 304 ADD Resource Usage IF ID EX MA WB time t0 t1 I1 I2 I1 t2 I3 I2 I1 t3 MA1 EX2 ID3 IF4 t4 WB1 MA2 nop nop IF5 t5 t3 I4 I3 I2 I1 t4 I5 nop nop I2 I1 t5 t6 CS152 Spring 2010 WB2 nop nop nop nop nop ID5 EX5 MA5 WB5 t6 t7 I5 nop I5 nop nop I5 I2 nop nop I5 nop February 2 2010 t7 pipeline bubble 13 Reducing Branch Penalty resolve in decode stage One pipeline bubble can be removed if an extra comparator is used in the Decode stage PCSrc pc 4 jabs rind br E Add nop 0x4 IR Add PC addr nop inst Inst Memory IR D we rs1 rs2 rd1 ws wd rd2 Zero detect on register file output GPRs Pipeline diagram now same as for jumps February 2 2010 CS152 Spring 2010 14 Branch Delay Slots expose control hazard to software Change the ISA semantics so that the instruction that follows a jump or branch is always executed gives compiler the flexibility to put in a useful instruction where normally a pipeline bubble would have resulted I1 I2 I3 I4 096 100 104 304 ADD BEQZ r1 200 ADD ADD Delay slot instruction executed regardless of branch outcome Other techniques include more advanced branch prediction which can dramatically reduce the branch penalty to come later February 2 2010 CS152 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