February 2, 2010 CS152, Spring 2010 CS 152 Computer Architecture and Engineering Lecture 5 - Pipelining II Krste Asanovic Electrical Engineering and Computer Sciences University of California at Berkeley http://www.eecs.berkeley.edu/~krste!http://inst.eecs.berkeley.edu/~cs152!February 2, 2010 CS152, Spring 2010 2 Last time in Lecture 4 • Pipelining increases clock frequency, while growing CPI more slowly, hence giving greater performance Time = Instructions Cycles Time Program Program * Instruction * Cycle Reduces because fewer logic gates on critical paths between flip-flops Increases because of pipeline bubbles • Pipelining of instructions is complicated by HAZARDS: – Structural hazards (two instructions want same hardware resource) – Data hazards (earlier instruction produces value needed by later instruction) – Control hazards (instruction changes control flow, e.g., branches or exceptions) • Techniques to handle hazards: – Interlock (hold newer instruction until older instructions drain out of pipeline and write back results) – Bypass (transfer value from older instruction to newer instruction as soon as available somewhere in machine) – Speculate (guess effect of earlier instruction)February 2, 2010 CS152, Spring 2010 3 Control Hazards • What do we need to calculate next PC? – For Jumps » Opcode, offset and PC – For Jump Register » Opcode and Register value – For Conditional Branches » Opcode, PC, Register (for condition), and offset – For all other instructions » Opcode and PC • have to know it’s not one of aboveFebruary 2, 2010 CS152, Spring 2010 4 time t0 t1 t2 t3 t4 t5 t6 t7 . . . . (I1) r1 ← (r0) + 10 IF1 ID1 EX1 MA1 WB1 (I2) r3 ← (r2) + 17 IF2 IF2 ID2 EX2 MA2 WB2 (I3) IF3 IF3 ID3 EX3 MA3 WB3 (I4) IF4 IF4 ID4 EX4 MA4 WB4 time t0 t1 t2 t3 t4 t5 t6 t7 . . . . IF I1 nop I2 nop I3 nop I4 ID I1 nop I2 nop I3 nop I4 EX I1 nop I2 nop I3 nop I4 MA I1 nop I2 nop I3 nop I4 WB I1 nop I2 nop I3 nop I4 PC Calculation Bubbles (assuming no branch delay slots for now) Resource Usage nop ⇒ pipeline bubbleFebruary 2, 2010 CS152, Spring 2010 5 Speculate next address is PC+4 I1 096 ADD I2 100 J 304 I3 104 ADD I4 304 ADD kill A jump instruction kills (not stalls) the following instruction stall How? I2 I1 104 IR IR PC addr inst Inst Memory 0x4 Add nop IR E M Add Jump? PCSrc (pc+4 / jabs / rind/ br)February 2, 2010 CS152, Spring 2010 6 Pipelining Jumps I1 096 ADD I2 100 J 304 I3 104 ADD I4 304 ADD kill I2 I1 104 stall IR IR PC addr inst Inst Memory 0x4 Add nop IR E M Add Jump? PCSrc (pc+4 / jabs / rind/ br) IRSrcD = Case opcodeD J, JAL ⇒ nop ... ⇒ IM To kill a fetched instruction -- Insert a mux before IR Any interaction between stall and jump? nop IRSrcD I2 I1 304 nopFebruary 2, 2010 CS152, Spring 2010 7 time t0 t1 t2 t3 t4 t5 t6 t7 . . . . IF I1 I2 I3 I4 I5 ID I1 I2 nop I4 I5 EX I1 I2 nop I4 I5 MA I1 I2 nop I4 I5 WB I1 I2 nop I4 I5 Jump Pipeline Diagrams time t0 t1 t2 t3 t4 t5 t6 t7 . . . . (I1) 096: ADD IF1 ID1 EX1 MA1 WB1 (I2) 100: J 304 IF2 ID2 EX2 MA2 WB2 (I3) 104: ADD IF3 nop nop nop nop (I4) 304: ADD IF4 ID4 EX4 MA4 WB4 Resource Usage nop ⇒ pipeline bubbleFebruary 2, 2010 CS152, Spring 2010 8 Pipelining Conditional Branches I1 096 ADD I2 100 BEQZ r1 +200 I3 104 ADD I4 304 ADD BEQZ? I2 I1 104 stall IR IR PC addr inst Inst Memory 0x4 Add nop IR E M Add PCSrc (pc+4 / jabs / rind / br) nop IRSrcD Branch condition is not known until the execute stage what action should be taken in the decode stage ? A Y ALU zero?February 2, 2010 CS152, Spring 2010 9 Pipelining Conditional Branches I1 096 ADD I2 100 BEQZ r1 +200 I3 104 ADD I4 304 ADD stall IR IR PC addr inst Inst Memory 0x4 Add nop IR E M Add PCSrc (pc+4 / jabs / rind / br) nop IRSrcD A Y ALU zero? If the branch is taken - kill the two following instructions - the instruction at the decode stage is not valid ⇒ stall signal is not valid I2 I1 108 I3 BEQZ? ?February 2, 2010 CS152, Spring 2010 10 Pipelining Conditional Branches I1 096 ADD I2 100 BEQZ r1 +200 I3 104 ADD I4 304 ADD stall IR IR PC addr inst Inst Memory 0x4 Add nop IR E M PCSrc (pc+4/jabs/rind/br) nop A Y ALU zero? I2 I1 108 I3 BEQZ? Jump? IRSrcD IRSrcE If the branch is taken - kill the two following instructions - the instruction at the decode stage is not valid ⇒ stall signal is not valid Add PCFebruary 2, 2010 CS152, Spring 2010 11 New Stall Signal stall = ( ((rsD =wsE).weE + (rsD =wsM).weM + (rsD =wsW).weW).re1D + ((rtD =wsE).weE + (rtD =wsM).weM + (rtD =wsW).weW).re2D ) . !((opcodeE=BEQZ).z + (opcodeE=BNEZ).!z) Don’t stall if the branch is taken. Why? Instruction at the decode stage is invalidFebruary 2, 2010 CS152, Spring 2010 12 Control Equations for PC and IR Muxes PCSrc = Case opcodeE BEQZ.z, BNEZ.!z ⇒ br ... ⇒ ## #Case opcodeD J, JAL ⇒ jabs JR, JALR ⇒ rind ... ⇒ pc+4 IRSrcD = Case opcodeE BEQZ.z, BNEZ.!z ⇒ nop ... ⇒ ## #Case opcodeD J, JAL, JR, JALR ⇒ nop ... ⇒ IM Give priority to the older instruction, i.e., execute stage instruction over decode stage instruction IRSrcE = Case opcodeE BEQZ.z, BNEZ.!z ⇒ nop ... ⇒ stall.nop + !stall.IRDFebruary 2, 2010 CS152, Spring 2010 13 time t0 t1 t2 t3 t4 t5 t6 t7 . . . . IF I1 I2 I3 I4 I5 ID I1 I2 I3 nop I5 EX I1 I2 nop nop I5 MA I1 I2 nop nop I5 WB I1 I2 nop nop I5 Branch Pipeline Diagrams (resolved in execute stage) time t0 t1 t2 t3 t4 t5 t6 t7 . . . . (I1) 096: ADD IF1 ID1 EX1 MA1 WB1 (I2) 100: BEQZ +200 IF2 ID2 EX2 MA2 WB2 (I3) 104: ADD IF3 ID3 nop nop nop (I4) 108: IF4 nop nop nop nop (I5) 304: ADD IF5 ID5 EX5 MA5 WB5 Resource Usage nop ⇒ pipeline bubbleFebruary 2, 2010 CS152, Spring 2010 14 • One pipeline bubble can be removed if an extra comparator is used in the Decode stage PC addr inst Inst Memory 0x4 Add IR IR nop E Add PCSrc (pc+4 / jabs / rind/ br) rd1 GPRs rs1 rs2 ws wd rd2 we nop Zero detect on register file output Pipeline diagram now same as for jumps D Reducing Branch Penalty (resolve in decode stage)February 2, 2010 CS152, Spring 2010 15 Branch Delay Slots (expose control
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