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Berkeley COMPSCI 152 - Divide, Floating Point, Pentium Bug

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CS152 Computer Architecture and Engineering Lecture 6 Divide, Floating Point, Pentium BugOutline of Today’s LectureRecap of Last Lecture: SummaryRecap: VHDL combinational exampleReview: MULTIPLY HARDWARE Version 3Review: Booth’s Algorithm InsightRadix-4 Modified Booth’s AlgorithmReview: Combinational Shifter from MUXesFunnel ShifterBarrel ShifterDivide: Paper & PencilDIVIDE HARDWARE Version 1Divide Algorithm Version 1Observations on Divide Version 1Slide 15DIVIDE HARDWARE Version 2Divide Algorithm Version 2Observations on Divide Version 2DIVIDE HARDWARE Version 3Divide Algorithm Version 3Observations on Divide Version 3Administrative MattersFloating-PointRecall Scientific NotationReview from Prerequisties: Floating-Point ArithmeticBasic Addition AlgorithmExtra Bits for roundingRounding DigitsSticky BitDenormalized NumbersInfinity and NaNsRadix-4 Modified Booth’s  Multiple representationsPentium BugPentium bug appearancePentium Bug Time linePentium jokesPentium conclusion: Dec. 21, 1994 $500M write-offSummary2/10/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec6.1CS152Computer Architecture and EngineeringLecture 6Divide, Floating Point, Pentium BugFeb 10, 1999John Kubiatowicz (http.cs.berkeley.edu/~kubitron)lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/2/10/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec6.2Outline of Today’s Lecture°Recap of Last Lecture and Introduction of Today’s Lecture (4 min.)°Divide (20 min.)°Questions and Administrative Matters (2 min.)°Floating-Point (25 min.)°Questions and Break (5 min.)°Pentium Bug (25min.)2/10/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec6.3Recap of Last Lecture: Summary°Intro to VHDL•entity = symbol, architecture ~ schematic, signals = wires•behavior can be higher level•x <= boolean_expression(A,B,C,D);°On-line Design Notebook•Open a window with editor, or our tool, => cut&paste°Multiply: successive refinement to see final design •32-bit Adder, 64-bit shift register, 32-bit Multiplicand Register•Booth’s algorithm to handle signed multiplies•There are algorithms that calculate many bits of multiply per cycle (see exercises 4.36 to 4.39 in COD)°Shifter: Best implemented with technology-specific methodologies°What’s Missing from MIPS is Divide & Floating Point Arithmetic: Next time the Pentium Bug2/10/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec6.4Recap: VHDL combinational exampleENTITY nandnor is GENERIC (delay: TIME := 1ns); PORT (a,b: IN VLBIT; x,y: OUT VLBIT)END nandnoreARCHITECTURE behavioral OF nandnor isBEGIN x <= a NOR b AFTER delay; y <= a NAND x AFTER delay;END behavioral;2/10/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec6.5Review: MULTIPLY HARDWARE Version 3°32-bit Multiplicand reg, 32-bit ALU, 64-bit Product reg (shift right), (0-bit Multiplier reg)Product(Multiplier)Multiplicand32-bit ALUWriteControl32 bits64 bitsShift Right“HI” “LO”2/10/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec6.6Review: Booth’s Algorithm InsightCurrent Bit Bit to the Right Explanation Example Op1 0 Begins run of 1s 0001111000 sub1 1 Middle of run of 1s 0001111000 none0 1 End of run of 1s 0001111000 add0 0 Middle of run of 0s 0001111000 noneOriginally for Speed (when shift was faster than add)°Replace a string of 1s in multiplier with an initial subtract when we first see a one and then later add for the bit afterthe last one0 1 1 1 1 0beginning of runend of runmiddle of run–1+ 10000011112/10/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec6.7Radix-4 Modified Booth’s AlgorithmCurrent Bit to the Explanation Example RecodeBits Right0 0 0 Middle of zeros 00 00 00 00 00 00 1 0 Single one 00 00 00 01 00 11 0 0 Begins run of 1s 00 01 11 10 00 -2 1 1 0 Begins run of 1s 00 01 11 11 00 -10 0 1 Ends run of 1s 00 00 11 11 00 10 1 1 Ends run of 1s 00 01 11 11 00 21 0 1 Isolated 0 00 11 10 11 00 -1 1 1 1 Middle of run 00 11 11 11 00 0°Same insight as one-bit Booth’s, simply adjust for alignment of 2 bits.°Allows multiplication 2-bits at a time.–1+ 10000011112/10/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec6.8Review: Combinational Shifter from MUXes°What comes in the MSBs?°How many levels for 32-bit shifter?°What if we use 4-1 Muxes ?10selABDBasic Building Block8-bit right shifter:101010101010101010101010101010101010101010101010S2 S1 S0A0A1A2A3A4A5A6A7R0R1R2R3R4R5R6R72/10/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec6.9Funnel ShifterXYR°Shift A by i bits (sa= shift right amount)°Logical: Y = 0, X=A, sa=i°Arithmetic? Y = Sign, X=A, sa=i°Rotate? Y = A, X=A, sa=i°Left shifts? Y = A, X=0, sa=32-iInstead Extract 32 bits of 64.Shift RightShift Right323232YXR2/10/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec6.10Barrel ShifterTechnology-dependent solutions: transistor per switchD3D2D1D0A6A5A4A3 A2 A1 A0SR0SR1SR2SR32/10/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec6.11Divide: Paper & Pencil 1001 QuotientDivisor 1000 1001010 Dividend–1000 10 101 1010 –1000 10 Remainder (or Modulo result)See how big a number can be subtracted, creating quotient bit on each stepBinary => 1 * divisor or 0 * divisorDividend = Quotient x Divisor + Remainder=> | Dividend | = | Quotient | + | Divisor |3 versions of divide, successive refinement2/10/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec6.12DIVIDE HARDWARE Version 1°64-bit Divisor reg, 64-bit ALU, 64-bit Remainder reg, 32-bit Quotient regRemainderQuotientDivisor64-bit ALUShift RightShift LeftWriteControl32 bits64 bits64 bits2/10/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec6.132b. Restore the original value by adding the Divisor register to the Remainder register, &place the sum in the Remainder register. Alsoshift the Quotient register to the left, setting the new least significant bit to 0.Divide Algorithm Version 1°Takes n+1 steps for n-bit Quotient & Rem.Remainder Quotient Divisor0000 0111 0000 0010 0000Test RemainderRemainder < 0Remainder  01. Subtract the Divisor register from the Remainder register, and place the result in the Remainder register.2a. Shift the Quotient register to the left setting the new rightmost bit to 1.3. Shift the Divisor register right1 bit.Done Yes: n+1 repetitions (n = 4 here)Start: Place Dividend in Remaindern+1repetition? No: < n+1 repetitions2/10/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec6.14Observations on Divide Version 1°1/2 bits in divisor always 0=> 1/2 of 64-bit adder is wasted => 1/2 of


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Berkeley COMPSCI 152 - Divide, Floating Point, Pentium Bug

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