Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38Slide 39Slide 40Slide 41Slide 42Slide 43Slide 44Slide 45Slide 46Slide 47Slide 48Slide 49Slide 50Slide 51Slide 52Slide 53Slide 54Slide 55Slide 56Slide 57Slide 58Slide 59CS 152 L15: Virtual Memory UC Regents Fall 2006 © UCB2006-10-19John Lazzaro (www.cs.berkeley.edu/~lazzaro)CS 152 Computer Architecture and EngineeringLecture 15 – Virtual Memorywww-inst.eecs.berkeley.edu/~cs152/TAs: Udam Saini and Jue SunUC Regents Fall 2006 © UCBCS 152 L15: Virtual Memory Last Time: Practical Cache DesignToCPUToLowerLevelMemoryToCPUToLowerLevelMemoryTagsBlocksAddrDinDoutAddrDinDoutState MachineControlControlControlCache design control is done by many loosely coupled state machines, including ...UC Regents Fall 2006 © UCBCS 152 L15: Virtual MemoryState machines for bus control ....Small, fast Large, slow FromCPUTo CPUFor reads,your state machine must: (1) sense REQ(2) latch Addr(3) create Wait(4) put Data Out on the bus.An example interface ... there are other possibilities.UC Regents Fall 2006 © UCBCS 152 L15: Virtual MemoryState machines for block fetch from DRAMOne request ...Many returns ...DRAM can be set up to request an N byte region starting at an arbitrary N+k within regionState machine challenges: (1) setting up correct block read mode (2) delivering correct word direct to CPU (3) putting all words in cache in right place.UC Regents Fall 2006 © UCBCS 152 L15: Virtual MemoryState machine for writeback to DRAMOne command ...Many bytes writtenState machine challenges: (1) putting cache block into correct location (2) what if a read or write wants to use DRAM before the burst is complete? Must stall ...UC Regents Fall 2006 © UCBCS 152 L15: Virtual Memory State machines to manage write bufferQ. Why a write buffer ? ProcessorCacheWrite BufferLower Level MemoryHolds data awaiting write-through to lower level memoryA. So CPU doesn’t stall Q. Why a buffer, why not just one register ?A. Bursts of writes arecommon.Q. Are Read After Write (RAW) hazards an issue for write buffer?A. Yes! Drain buffer before next read, or check write buffers.Solution: add a “write buffer” to cache datapath On reads, state machine checks cache and write buffer -- what if word was removed from cache before lower-level write? On writes, state machine stalls for full write buffer, handles write buffer duplicates.UC Regents Fall 2006 © UCBCS 152 L15: Virtual Memory Don’t design one big state machine!!!ToCPUToLowerLevelMemoryToCPUToLowerLevelMemoryTagsBlocksAddrDinDoutAddrDinDoutState MachineControlControlControlFocus on the high-level state machine structure early!UC Regents Fall 2006 © UCBCS 152 L15: Virtual MemoryToday’s Lecture - Virtual MemoryVirtual address spacesPage table layoutTLB design optionsVirtual machinesUC Regents Fall 2006 © UCBCS 152 L15: Virtual MemoryThe Limits of Physical AddressingCPU MemoryA0-A31 A0-A31D0-D31 D0-D31“Physical addresses” of memory locations DataAll programs share one address space: The physical address spaceNo way to prevent a program from accessing any machine resourceMachine language programs must beaware of the machine organization Where we are in CS 152 ...CS 152 L15: Virtual Memory UC Regents Fall 2006 © UCBApple II: A physically addressed machine Apple ][ (1977)UC Regents Fall 2006 © UCBCS 152 L15: Virtual MemoryThe Limits of Physical AddressingCPU MemoryA0-A31 A0-A31D0-D31 D0-D31“Physical addresses” of memory locations DataAll programs share one address space: The physical address spaceNo way to prevent a program from accessing any machine resourceMachine language programs must beaware of the machine organization Programming the Apple ][ ...UC Regents Fall 2006 © UCBCS 152 L15: Virtual MemorySolution: Add a Layer of IndirectionCPU MemoryA0-A31 A0-A31D0-D31 D0-D31DataUser programs run in an standardizedvirtual address spaceAddress Translation hardware managed by the operating system (OS)maps virtual address to physical memory“Physical Addresses”AddressTranslationVirtual Physical“Virtual Addresses”Hardware supports “modern” OS features:Protection, Translation, SharingUC Regents Fall 2006 © UCBCS 152 L15: Virtual MemoryMIPS R4000: Address Space ModelProcess AAddressError2 GB0231232- 1Process BAddressError2 GB0231232- 1Process A and B have independent address spacesASID = 12 ASID = 13ASID = Address Space IdentifierWhen Process A writes its address 9, it writes to a different physical memory location than Process B’s address 9May only be accessed by kernel/supervisorTo let Process A and B share memory, OS maps parts of ASID 12 and ASID 13 to the same physical memory locations.All address spacesuse a standard memory mapStill works (slowly!) if a process accesses more virtual memory than the machine has physical memoryUC Regents Fall 2006 © UCBCS 152 L15: Virtual MemoryMIPS R4000: Who’s Running on the CPU?System Control Registers User cannot write supervisor/kernel bits. Supervisor cannot write kernel bit.User cannot change address translation configurationStatus (12): Indicatesuser, supervisor, or kernel modeEntryLo0 (2): 8-bit ASID field codes virtualaddress space ID.UC Regents Fall 2006 © UCBCS 152 L15: Virtual MemoryMIPS Address Translation: How it works“Physical Addresses”CPU MemoryA0-A31 A0-A31D0-D31 D0-D31DataTLB also contains ASID andkernel/supervisor bits for virtual addressVirtual Physical“Virtual Addresses”TranslationLook-AsideBuffer(TLB)Translation Look-Aside Buffer (TLB)A small fully-associative cache of mappings from virtual to physical addressesFast common case: Virtual address is in TLB, process has permission to read/write it. What is the table ofmappings that it caches?UC Regents Fall 2006 © UCBCS 152 L15: Virtual MemoryPage tables encode virtual address spacesA machine usually supportspages of a few sizes(MIPS R4000):PhysicalMemory SpaceA valid page table entry codes physical memory “frame” address for the pageA virtual address spaceis divided into blocksof memory called pagesframeframeframeframeA page table is indexed by a virtual addressvirtual address Page Table(One per ASID)OS manages the page table for each ASIDUC Regents Fall 2006 © UCBCS 152 L15: Virtual MemoryV=0 pages either reside on disk or have not
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