CS 152 Computer Architecture and Engineering Lecture 15 Virtual Memory 2006 10 19 John Lazzaro www cs berkeley edu lazzaro TAs Udam Saini and Jue Sun www inst eecs berkeley edu cs152 CS 152 L15 Virtual Memory UC Regents Fall 2006 UCB Last Time Practical Cache Design Cache design control is done by many loosely coupled state machines including To CPU State Machine Control Control Control Addr To CPU CS 152 L15 Virtual Memory Din Dout Addr Blocks Tags Din Dout To Lower Level Memory To Lower Level Memory UC Regents Fall 2006 UCB State machines for bus control For reads your state machine must Small fast Large slow 1 sense REQ 2 latch Addr 3 create Wait 4 put Data Out on the From bus CPU To CPU An example interface there are other CS 152 L15 Virtual Memory possibilities UC Regents Fall 2006 UCB State machines for block fetch from DRAM One request DRAM can be set up to request an N byte region starting at an arbitrary N k within region Many returns State machine challenges 1 setting up correct block read mode 2 delivering correct word direct to CPU 3 putting all CS 152 L15 Virtual Memory UC Regents Fall 2006 UCB State machine for writeback to DRAM One command Many bytes writte n State machine challenges 1 putting cache block into correct location 2 what if a read or write wants to use DRAM CS 152 L15 Virtual Memory UC Regents Fall 2006 UCB State machines to manage write buffer Solution add a write buffer to cache datapath Lower Cache Processor Level Memory Write Buffer Holds data awaiting write through to lower level memory Q Why a write A So CPU doesn t buffer stall Q Why a buffer A Bursts of writes why not just one are register common Q Are Read After A Yes Drain Write RAW buffer before next hazards an issue read or check write buffer buffers On for reads state machinewrite checks cache and write buffer what if word was removed from cache before lower level write On writes state machine stalls for full write buffer handles write CS 152 L15 Virtual Memory UC Regents Fall 2006 UCB Don t design one big state machine Focus on the high level state machine structure early To CPU State Machine Control Control Control Addr To CPU CS 152 L15 Virtual Memory Din Dout Addr Blocks Tags Din Dout To Lower Level Memory To Lower Level Memory UC Regents Fall 2006 UCB Today s Lecture Virtual Memory Virtual address spaces Page table layout TLB design options Virtual machines CS 152 L15 Virtual Memory UC Regents Fall 2006 UCB The Limits of Physical Addressing Physical addresses of memory locations A0 A31 CPU A0 A31 Where we are in CS 152 D0 D31 Memory D0 D31 Data All programs share one address space The physical address space Machine language programs must be aware of the machine organization No way to prevent a program from accessing any machine resource CS 152 L15 Virtual Memory UC Regents Fall 2006 UCB Apple II A physically addressed machine Apple 1977 CS 152 L15 Virtual Memory UC Regents Fall 2006 UCB The Limits of Physical Addressing Physical addresses of memory locations A0 A31 CPU A0 A31 Programming the Apple D0 D31 Memory D0 D31 Data All programs share one address space The physical address space Machine language programs must be aware of the machine organization No way to prevent a program from accessing any machine resource CS 152 L15 Virtual Memory UC Regents Fall 2006 UCB Solution Add a Layer of Indirection Physical Addresses Virtual Addresses A0 A31 Virtual Physical Address Translation CPU D0 D31 A0 A31 Memory D0 D31 Data User programs run in an standardized virtual address space Address Translation hardware managed by the operating system OS maps virtual address to physical memory Hardware supports modern OS features Protection Translation Sharing CS 152 L15 Virtual Memory UC Regents Fall 2006 UCB MIPS R4000 Address Space Model Process A ASID 12 32 2 1 Address Error 2 ASID Address Space Identifier Process A and B have independent address spaces 2 GB 0 ASID 13 32 2 1 All address spaces use a standard memory map May only be accessed by kernel supervisor 31 Process B When Process A writes its address 9 it writes to a different physical memory location than Process B s address 9 To let Process A and B share memory OS maps parts of ASID 12 and ASID 13 to the same physical memory locations Address Error 2 31 2 GB 0 Still works slowly if a process accesses more virtual memory than the machine has physical memory CS 152 L15 Virtual Memory UC Regents Fall 2006 UCB MIPS R4000 Who s Running on the CPU System Control Registers Status 12 Indicates user supervisor or kernel mode EntryLo0 2 8 bit ASID field codes virtual address space ID User cannot write supervisor kernel bits Supervisor cannot write kernel bit User cannot change address translation configuration CS 152 L15 Virtual Memory UC Regents Fall 2006 UCB MIPS Address Translation How it works Physical Addresses Virtual Addresses A0 A31 Virtual CPU D0 D31 Data Physical Translation Look Aside Buffer TLB A0 A31 Memory D0 D31 What is the Translation Look Aside Buffer TLB table of A small fully associative cache of mappin mappings from virtual to physical addressesgs that it TLB also contains ASID and caches kernel supervisor bits for virtual address Fast common case Virtual address is in TLB process has permission to read write it CS 152 L15 Virtual Memory UC Regents Fall 2006 UCB Page tables encode virtual address spaces Page Table One per ASID Physical Memory Space frame frame frame frame virtual address OS manages the page table for each ASID A virtual address space is divided into blocks of memory called pages A machine usually supports pages of a few sizes MIPS R4000 A page table is indexed by a virtual address A valid page table entry codes physical memory frame address for the page CS 152 L15 Virtual Memory UC Regents Fall 2006 UCB The TLB caches page table entries In this example physical and virtual pages must be the same size TLB caches page table entries virtual address page Physic al frame addres s for ASID off Page Table 2 0 1 3 TLB frame page 2 2 0 5 CS 152 L15 Virtual Memory physical address page off MIPS handles TLB misses in software random replacement Other V 0 pages either reside on disk or have not yet been allocated OS handles UC Regents Fall 2006 UCB V 0 Page tables may not fit in memory A table for 4KB pages for a 32 bit address space has 1M entries Each process needs its own address space Two level Page Tables 32 bit virtual address 31 22 21 12 11 0 P1 index P2 index Page Offset Top level table wired in main memory Subset
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