CS 152 Computer Architecture and Engineering Lecture 9 Designing a Multicycle Processor February 26 2003 John Kubiatowicz www cs berkeley edu kubitron lecture slides http inst eecs berkeley edu cs152 2 26 03 UCB Spring 2003 CS152 Kubiatowicz Recap Processor Design is a Process Bottom up assemble components in target technology to establish critical timing Top down specify component behavior from high level requirements Iterative refinement establish partial solution expand and improve Instruction Set Architecture processor datapath Reg File Mux ALU control Reg Cells 2 26 03 Mem Decoder Sequencer Gates UCB Spring 2003 CS152 Kubiatowicz Recap A Single Cycle Datapath Instruction 31 0 1 Mux 0 RegWr 5 5 Rs 5 Rt Rs ALUctr busA 0 1 32 Imm16 MemtoReg Data In 32 ALUSrc 0 32 Clk WrEn Adr 32 Mux 16 Extender imm16 32 Mux 32 Clk Rw Ra Rb 32 32 bit Registers busB 32 Rd Equal MemWr ALU busW Rt 0 15 Clk 11 15 RegDst Rt 21 25 Rd Instruction Fetch Unit 16 20 nPC sel 1 Data Memory ExtOp 2 26 03 UCB Spring 2003 CS152 Kubiatowicz Recap The Truth Table for the Main Control op 6 Main Control RegDst ALUSrc func 6 ALUop ALU Control Local ALUctr 3 3 op RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUop Symbolic ALUop 2 ALUop 1 ALUop 0 2 26 03 00 0000 R type 1 0 0 1 0 0 0 x R type 1 0 0 00 1101 10 0011 10 1011 00 0100 00 0010 ori lw sw beq jump 0 0 x x x 1 1 1 0 x 0 1 x x x 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 x x Or Add Add Subtract xxx 0 0 0 x 0 1 0 0 x 0 0 0 0 x 1 UCB Spring 2003 CS152 Kubiatowicz Recap PLA Implementation of the Main Control op 5 op 5 0 R type op 5 0 ori op 5 0 lw op 5 0 sw op 5 0 beq jump op 0 RegWrite ALUSrc RegDst MemtoReg MemWrite Branch Jump ExtOp ALUop 2 ALUop 1 ALUop 0 2 26 03 UCB Spring 2003 CS152 Kubiatowicz Recap Systematic Generation of Control Control Logic Store PLA ROM microinstruction Conditions Instruction Decode OPcode Control Points Datapath In our single cycle processor each instruction is realized by exactly one control command or microinstruction in general the controller is a finite state machine microinstruction can also control sequencing see later 2 26 03 UCB Spring 2003 CS152 Kubiatowicz The Big Picture Where are We Now The Five Classic Components of a Computer Processor Input Control Memory Datapath Output Today s Topic Designing the Datapath for the Multiple Clock Cycle Datapath 2 26 03 UCB Spring 2003 CS152 Kubiatowicz Abstract View of our single cycle processor Main Control op Result Store MemWr RegDst RegWr Reg Wrt Data Mem Mem Access Ext ExtOp ALUSrc ALUctr Equal Register Fetch Instruction Fetch PC nPC sel Next PC ALU MemRd MemWr ALU control fun looks like a FSM with PC as state 2 26 03 UCB Spring 2003 CS152 Kubiatowicz What s wrong with our CPI 1 processor Arithmetic Logical PC Inst Memory Reg File mux ALU mux setup Load PC Inst Memory ALU Data Mem Store PC mux Reg File Critical Path Inst Memory Reg File ALU Data Mem Branch PC Inst Memory Reg File mux cmp mux setup mux Long Cycle Time All instructions take as much time as the slowest Real memory is not as nice as our idealized memory cannot always get the job done in one short cycle 2 26 03 UCB Spring 2003 CS152 Kubiatowicz Memory Access Time Physics fast memories are small large memories are slow Storage Array selected word line storage cell address bit line address decoder sense amps Processor Cache proc bus Use a hierarchy of memories L2 Cache 1 time period 2 3 time periods 2 26 03 UCB Spring 2003 mem bus question register file vs memory memory 20 50 time periods CS152 Kubiatowicz Reducing Cycle Time Cut combinational dependency graph and insert register latch Do same work in two fast cycles rather than one slow one May be able to short circuit path and remove some components for some instructions storage element storage element Acyclic Combinational Logic Acyclic Combinational Logic A storage element Acyclic Combinational Logic B storage element 2 26 03 UCB Spring 2003 storage element CS152 Kubiatowicz Worst Case Timing Load Clk PC Old Value Clk to Q New Value Instruction Memoey Access Time New Value Rs Rt Rd Op Func Old Value ALUctr Old Value ExtOp Old Value New Value ALUSrc Old Value New Value MemtoReg Old Value New Value RegWr Old Value New Value busA busB Delay through Control Logic New Value Register Write Occurs Register File Access Time New Value Old Value Delay through Extender Mux Old Value New Value ALU Delay Address Old Value New Value Data Memory Access Time busW 2 26 03 Old Value UCB Spring 2003 New CS152 Kubiatowicz Basic Limits on Cycle Time Next address logic PC branch PC offset PC 4 Instruction Fetch InstructionReg Mem PC Register Access A R rs ALU operation UCB Spring 2003 Result Store MemWr RegDst RegWr Reg File Data Mem MemRd MemWr ALUctr Exec Mem Access Operand Fetch Instruction Fetch PC ExtOp nPC sel Next PC 2 26 03 ALUSrc Control R A B CS152 Kubiatowicz 2 26 03 UCB Spring 2003 Place enables on all registers Result Store MemWr MemRd MemWr RegDst RegWr Reg File Data Mem Exec Mem Access ALUctr ALUSrc ExtOp Operand Fetch Instruction Fetch PC Next PC nPC sel Equal Partitioning the CPI 1 Datapath Add registers between smallest steps CS152 Kubiatowicz 2 26 03 ExtOp Equal B UCB Spring 2003 S Reg File RegDst RegWr MemToReg MemRd MemWr ALUctr Ext ALUSrc ALU A Result Store Reg File Mem Access IR nPC sel E Data Mem Operand Fetch Instruction Fetch PC Next PC Example Multicycle Datapath M Critical Path CS152 Kubiatowicz Administrative Issues Read Chapter 5 This lecture and next one slightly different from the book Midterm two weeks from today Wednesday 3 12 5 30pm to 8 30pm location TBA No class on that day Pencil calculator one 8 5 x 11 both sides of handwritten notes Sit in every other chair every other row Meet at LaVal s pizza after the midterm 2 26 03 UCB Spring 2003 CS152 Kubiatowicz Recall Step by step Processor Design Step 1 ISA Logical Register Transfers Step 2 Components of the Datapath Step 3 RTL Components Datapath Step 4 Datapath Logical RTs Physical RTs Step 5 Physical RTs Control 2 26 03 UCB Spring 2003 CS152 Kubiatowicz Step 4 R rtype add sub Logical Register Transfer Physical Register Transfers inst Logical Register Transfers ADDU R rd R rs R rt PC PC 4 inst Physical Register Transfers Time IR MEM pc ADDU A R rs B R rt S A B R rd S PC PC 4 B UCB Spring 2003 Reg File S Mem Access Exec Reg File IR Inst Mem A M Data Mem 2 …
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