Recap Who Cares About the Memory Hierarchy Processor DRAM Memory Gap latency CS152 Computer Architecture and Engineering Lecture 18 Proc 60 yr Moore s Law 2X 1 5yr Processor Memory Performance Gap grows 50 year DRAM DRAM 9 yr 2X 10 yrs Memory and Caches April 7 1999 John Kubiatowicz http cs berkeley edu kubitron Performance 1000 CPU 100 10 1980 1981 1982 1983 1984 1985 1986 1987 1988 1989 1990 1991 1992 1993 1994 1995 1996 1997 1998 1999 2000 1 lecture slides http www inst eecs berkeley edu cs152 4 7 99 UCB Spring 1999 CS152 Kubiatowicz Lec18 1 Recap Static RAM Cell 0 bit CS152 Kubiatowicz Lec18 2 word word row select 1 row select Write 1 Drive bit line 2 Select row 1 Read bit Write 1 Drive bit lines bit 1 bit 0 2 Select row bit 1 Precharge bit line to Vdd 2 Select row bit 3 Cell and bit line share charges Very small voltage changes on the bit line 4 Sense fancy sense amp Can detect changes of 1 million electrons 5 Write restore the value bit replaced with pullup to save area Read 1 Precharge bit and bit to Vdd 2 Select row 3 Cell pulls one line low 4 Sense amp on column detects difference between bit and bit 4 7 99 UCB Spring 1999 Recap 1 Transistor Memory Cell DRAM 6 Transistor SRAM Cell 0 Time 4 7 99 UCB Spring 1999 CS152 Kubiatowicz Lec18 3 Refresh 1 Just do a dummy read to every cell 4 7 99 UCB Spring 1999 CS152 Kubiatowicz Lec18 4 Recap Memory Hierarchy of a Modern Computer System Recap Memory Systems By taking advantage of the principle of locality Two Different Types of Locality Present the user with as much memory as is available in the cheapest technology Provide access at the speed offered by the fastest technology Temporal Locality Locality in Time If an item is referenced it will tend to be referenced again soon Spatial Locality Locality in Space If an item is referenced items whose addresses are close by tend to be referenced soon Processor By taking advantage of the principle of locality Control On Chip Cache Registers Datapath Second Level Cache SRAM Main Memory DRAM Secondary Storage Disk Present the user with as much memory as is available in the cheapest technology Tertiary Storage Disk Provide access at the speed offered by the fastest technology DRAM is slow but cheap and dense Good choice for presenting the user with a BIG memory system SRAM is fast but expensive and not very dense Speed ns 1s Size bytes 100s 4 7 99 10s 100s Ks Ms 10 000 000s 10 000 000 000s 10s sec 10s ms Ts Gs UCB Spring 1999 CS152 Kubiatowicz Lec18 5 The Big Picture Where are We Now Good choice for providing the user FAST access time 4 7 99 CS152 Kubiatowicz Lec18 6 UCB Spring 1999 Classical DRAM Organization square bit data lines The Five Classic Components of a Computer Processor r o w Input Control Memory Datapath d e c o d e r Output Today s Topics Recap last lecture Each intersection represents a 1 T DRAM Cell RAM Cell Array word row select Continue discussion of DRAM Cache Review Advanced Cache row address Virtual Memory Protection data TLB 4 7 99 Column Selector I O Circuits UCB Spring 1999 CS152 Kubiatowicz Lec18 7 Column Address Row and Column Address together Select 1 bit a time 4 7 99 UCB Spring 1999 CS152 Kubiatowicz Lec18 8 DRAM physical organization 4 Mbit DRAM logical organization 4 Mbit Column Decoder Sense Amps I O 11 Q Memory Array 2 048 x 2 048 D Block Row Dec 9 512 I O I O CS152 Kubiatowicz Lec18 9 4 7 99 Logic Diagram of a Typical DRAM A 9 CAS L WE L 8 Every DRAM access begins at 8 I Os CS152 Kubiatowicz Lec18 10 RAS L The assertion of the RAS L 2 ways to read early or late v CAS D Din and Dout are combined D CAS L WE L is asserted Low OE L is disasserted High D serves as the data input pin WE L is disasserted High OE L is asserted Low D is the data output pin CAS L A WE L 256K x 8 DRAM 9 OE L D 8 DRAM Read Cycle Time RAS L A Row Address Col Address Junk Row Address Col Address Junk WE L OE L Row and column addresses share the same pins A D High Z RAS CAS edge sensitive CS152 Kubiatowicz Lec18 11 Junk Data Out High Z Read Access Time RAS L goes low Pins A are latched in as row address CAS L goes low Pins A are latched in as column address UCB Spring 1999 Block 3 UCB Spring 1999 Control Signals RAS L CAS L WE L OE L are all active low 4 7 99 Q DRAM Read Timing OE L 256K x 8 DRAM Block Row Dec 9 512 I O I O Block 0 UCB Spring 1999 Block Row Dec 9 512 2 Square root of bits per RAS CAS RAS L Block Row Dec 9 512 Storage Word Line Cell 4 7 99 I O I O D Row Address A0 A10 8 I Os I O I O Column Address Early Read Cycle OE L asserted before CAS L 4 7 99 Data Out Output Enable Delay Late Read Cycle OE L asserted after CAS L UCB Spring 1999 CS152 Kubiatowicz Lec18 12 DRAM Write Timing Main Memory Performance Every DRAM access begins at RAS L The assertion of the RAS L 2 ways to write early or late v CAS CAS L A WE L 256K x 8 DRAM 9 OE L D 8 DRAM WR Cycle Time RAS L CAS L A Row Address Col Address Junk Row Address Col Address Wide Junk OE L WE L D Junk Data In Junk WR Access Time Early Wr Cycle WE L asserted before CAS L 4 7 99 Data In Junk Simple WR Access Time CS152 Kubiatowicz Lec18 13 4 7 99 Main Memory Performance CS152 Kubiatowicz Lec18 14 UCB Spring 1999 Increasing Bandwidth Interleaving Cycle Time Access Time CPU Cache Bus 1 word Memory N Modules 4 Modules example is word interleaved CPU Cache Bus Memory same width 32 bits Late Wr Cycle WE L asserted after CAS L UCB Spring 1999 Interleaved CPU Mux 1 word Mux Cache Bus Memory N words Alpha 64 bits 256 bits Access Pattern without Interleaving CPU DRAM Read Write Cycle Time DRAM Read Write Access Time D1 available Start Access for D1 2 1 why DRAM Read Write Cycle Time How frequent can you initiate an access Analogy A little kid can only ask his father for money on Saturday Start Access for D2 Memory Bank 0 Access Pattern with 4 way Interleaving CPU DRAM Read Write Access Time DRAM Bandwidth Limitation analogy What happens if he runs out of money on Wednesday UCB Spring 1999 CS152 Kubiatowicz Lec18 15 Memory Bank 1 Memory Bank 2 Access Bank 0 How …
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