CS152 Computer Architecture and Engineering Lecture 7 Designing a Single Cycle Datapath February 18 2004 Review Sequential Logic Non blocking assignments Must be careful mixing zero time blocking assignments and edge triggering Probably won t do what you expect when connecting it to other things module FF CLK Q D input D CLK output Q reg Q always posedge CLK Q D endmodule FF Good Doesn t output until after edge John Kubiatowicz www cs berkeley edu kubitron lecture slides http inst eecs berkeley edu cs152 2 18 03 CS152 Kubiatowicz Lec7 1 UCB Spring 2004 Review MULTIPLY HARDWARE Version 3 Probably Not what you Expect Hold time of 5 units glitches 5 units ignored 2 19 03 module FF CLK Q D input D CLK output Q reg Q always posedge CLK Q 5 D endmodule FF Good Outputs 5 units after edge module FF CLK Q D input D CLK output Q reg Q always posedge CLK 5 Q D endmodule FF UCB Spring 2003 CS152 Kubiatowicz Lec7 2 Divide can use almost same hardware From Book 32 bit Multiplicand reg 32 bit ALU 64 bit Product reg shift right 0 bit Multiplier reg 32 bit Divisor reg 32 bit ALU 64 bit Remainder reg 0 bit Quotient reg Divisor 32 bits Multiplicand 32 bits 32 bit ALU HI 32 bit ALU LO Shift Left Remainder Quotient HI LO Shift Right Product Multiplier 64 bits 64 bits Control Write Control Write Multiplication and Division can use same hardware 2 19 03 UCB Spring 2003 CS152 Kubiatowicz Lec7 3 2 19 03 UCB Spring 2003 CS152 Kubiatowicz Lec7 4 Review Booth s Algorithm Alternate representation end of run middle of run beginning of run 0 1 1 1 1 0 Current Bit Bit to the Right Explanation Example Op 1 0 Begins run of 1s 0001111000 sub 1 1 1 Middle of run of 1s 0001111000 none 0 0 1 End of run of 1s 0001111000 add 1 0 0 Middle of run of 0s 0001111000 none 0 MIPS logical instructions Instruction Example Meaning and and 1 2 3 or or 1 2 3 xor xor 1 2 3 nor nor 1 2 3 and immediate andi 1 2 10 or immediate ori 1 2 10 xor immediate xori 1 2 10 shift left logical sll 1 2 10 shift right logical srl 1 2 10 shift right arithm sra 1 2 10 shift left logical sllv 1 2 3 shift right logical srlv 1 2 3 shift right arithm srav 1 2 3 Comment 1 2 3 1 2 3 1 2 3 1 2 3 1 2 10 1 2 10 1 2 10 1 2 10 1 2 10 1 2 10 1 2 3 1 2 3 1 2 3 3 reg operands Logical AND 3 reg operands Logical OR 3 reg operands Logical XOR 3 reg operands Logical NOR Logical AND reg constant Logical OR reg constant Logical XOR reg constant Shift left by constant Shift right by constant Shift right sign extend Shift left by variable Shift right by variable Shift right arith by variable Examples 8 bits 3 11111101 00000 1 1 1 4 2 1 14 00001110 000100 1 0 16 2 23 00010111 001 1 100 1 32 16 8 1 2 19 03 UCB Spring 2003 CS152 Kubiatowicz Lec7 5 Shifters 2 19 03 CS152 Kubiatowicz Lec7 6 UCB Spring 2003 Barrel Shifter Technology dependent solutions transistor per switch Two kinds SR3 logical RIGHT OR LEFT value shifted in is always 0 0 msb lsb lsb SR1 SR0 D3 0 D2 arithmetic RIGHT ONLY sign extend msb SR2 A6 0 D1 A5 Note these are single bit shifts A given instruction might request 0 to 32 bits to be shifted 2 19 03 UCB Spring 2003 CS152 Kubiatowicz Lec7 7 D0 A4 A3 2 19 03 A2 A1 UCB Spring 2003 A0 CS152 Kubiatowicz Lec7 8 The Big Picture Where are We Now The Five Classic Components of a Computer Processor Input Control Memory The Big Picture The Performance Perspective Performance of a machine is determined by CPI Instruction count Clock cycle time Clock cycles per instruction Inst Count Datapath Output Today s Topic Design a Single Cycle Processor machine design inst set design L1 2 2 19 03 Arithmetic L4 6 technology L3 UCB Spring 2003 CS152 Kubiatowicz Lec7 9 How to Design a Processor step by step Cycle Time Processor design datapath and control will determine Clock cycle time Clock cycles per instruction Today Single cycle processor Advantage One clock cycle per instruction Disadvantage long cycle time 2 19 03 CS152 Kubiatowicz Lec7 10 UCB Spring 2003 The MIPS Instruction Formats 1 Analyze instruction set datapath requirements the meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers possibly more datapath must support each register transfer All MIPS instructions are 32 bits long The three instruction formats 31 26 op R type 6 bits I type 31 op J type 31 16 rt 5 bits 26 5 bits 21 rs 6 bits 2 Select set of datapath components and establish clocking methodology 21 rs 5 bits 4 Analyze implementation of each instruction to determine setting of control points that effects the register transfer 5 Assemble the control logic 6 0 shamt funct 5 bits 5 bits 6 bits 16 0 immediate rt 5 bits 16 bits 26 0 op target address 6 bits 3 Assemble datapath meeting the requirements 11 rd 26 bits The different fields are op operation of the instruction rs rt rd the source and destination register specifiers shamt shift amount funct selects the variant of the operation in the op field address immediate address offset or immediate value target address target address of the jump instruction 2 19 03 UCB Spring 2003 CS152 Kubiatowicz Lec7 11 2 19 03 UCB Spring 2003 CS152 Kubiatowicz Lec7 12 Step 1a The MIPS lite Subset for today Logical Register Transfers RTL gives the meaning of the instructions ADD and SUB addU rd rs rt 31 26 op 21 rs 6 bits 16 rt 5 bits 5 bits 11 6 0 rd shamt funct 5 bits 5 bits 6 bits All start by fetching the instruction op rs rt rd shamt funct MEM PC subU rd rs rt OR Immediate ori rt rs imm16 LOAD and STORE Word lw rt rs imm16 sw rt rs imm16 31 26 op 31 6 bits 26 op 31 beq rs rt imm16 5 bits 21 op 5 bits 16 5 bits 16 bits 0 immediate 5 bits 21 rs 6 bits 0 op rs rt Imm16 16 bits 16 rt 0 immediate 5 bits 16 bits inst Register Transfers ADDU R rd R rs R rt PC PC 4 SUBU R rd R rs R rt PC PC 4 ORi R rt R rs zero ext Imm16 PC PC 4 LOAD R rt MEM R rs sign ext Imm16 PC PC 4 STORE MEM R rs sign ext Imm16 R rt PC PC 4 BEQ 2 19 03 MEM PC immediate rt 5 bits 26 16 rt rs 6 bits BRANCH 21 …
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