Outline of Today s Lecture CS152 Computer Architecture and Engineering Lecture 7 Recap 5 minutes Finish on Floating Point Design a processor step by step Designing a Single Cycle Datapath Requirements of the Instruction Set Questions and Administrative Matters 5 minutes Components and Clocking September 22 2001 John Kubiatowicz http cs berkeley edu kubitron Assembling an Adequate Datapath Break 5 minutes lecture slides http www inst eecs berkeley edu cs152 9 22 01 UCB Fall 2001 CS152 Kubiatowicz Lec7 1 Controling the datapath 9 22 01 Review DIVIDE HARDWARE Version 3 UCB Fall 2001 Divide Algorithm Version 3 example 7 2 Remainder 32 bit Divisor reg 32 bit ALU 64 bit Remainder reg 0 bit Quotient reg Divisor 32 bits 32 bit ALU HI LO Shift Left Remainder Quotient 64 bits Control Write Multiplication and Division can use same hardware 9 22 01 UCB Fall 2001 CS152 Kubiatowicz Lec7 2 CS152 Kubiatowicz Lec7 3 0 1 2 3 1 2 3 1 2 3 1 2 3 E 0000 0000 1110 0000 0001 1111 0001 0011 0001 0001 0011 0001 0001 0010 0001 9 22 01 0111 1110 1110 1110 1100 1100 1100 1000 1000 1000 0001 0001 0001 0011 0011 Divisor 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 Initial Shift Try to subtract Can t Add back Shift in 0 Try to subtract Can t Add back Shift in 0 Try to subtract Success Shift in 1 Try to subtract Success Shift in 1 Correct remainder UCB Fall 2001 CS152 Kubiatowicz Lec7 4 Recall What is in a number Non restoring version Remainder 0 1 3 1 3 1 3 1 3 E 0000 0000 1110 1101 1111 1111 0001 0011 0001 0010 0001 0111 1110 1110 1100 1100 1000 1000 0001 0001 0011 0011 What can be represented in N bits Divisor 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 Initial Shift Try to subtract Negative Shift in Try to add neg Negative Shift in Try to Add Positive Shift in Try to subtract Positive Shift in Correct remainder Unsigned 0 to 2N 1 2s Complement 2N 1 to 2N 1 1 1s Complement 2N 1 1 to 2N 1 1 0 Excess M E e M 2 M to 2 N M 1 1 BCD 0 to 10N 4 1 1 But what about very large numbers very small number 0 9 349 398 989 787 762 244 859 087 678 0 0000000000000000000000045691 rationals irrationals Insight Divisor 2 Divisor Divisor 2 3 2 e transcendentals 9 22 01 CS152 Kubiatowicz Lec7 5 UCB Fall 2001 Review Recall Scientific Notation 23 6 02 x 10 UCB Fall 2001 CS152 Kubiatowicz Lec7 6 Review from Prerequisties Floating Point Arithmetic Representation of floating point numbers in IEEE 754 standard 1 8 23 single precision E sign S M exponent Sign magnitude decimal point Mantissa 9 22 01 1 673 x 10 24 mantissa exponent sign magnitude normalized excess 127 binary integer binary significand w hidden integer bit 1 M actual exponent is e E 127 radix base 0 E 255 Sign magnitude IEEE F P 1 M x 2 S E 127 N 1 2 1 M e 127 0 0 00000000 0 0 1 5 1 01111111 10 0 Issues Arithmetic Representation Normal form Range and Precision Rounding Exceptions e g divide by zero overflow underflow Magnitude of numbers that can be represented is in the range 2 Properties negation inversion if A z B then A B z 0 CS152 Kubiatowicz UCB Fall 2001 1 0 to which is approximately 38 to 1 8 x 10 Errors 9 22 01 126 Lec7 7 2 127 2 2 23 3 40 x 10 38 integer comparison valid on IEEE Fl Pt numbers of same sign 9 22 01 UCB Fall 2001 CS152 Kubiatowicz Lec7 8 Extra Bits for rounding Basic Addition Algorithm Multiply issues For addition or subtraction this translates into the following steps Floating Point numbers are like piles of sand every time you move one you lose a little sand but you pick up a little dirt 1 compute Ye Xe getting ready to align binary point Xe Ye 2 right shift Xm that many positions to form Xm 2 Xe Ye 3 compute Xm 2 Ym How many extra bits IEEE As if computed the result exactly and rounded Addition 1 xxxxx if representation demands normalization then normalization step follows 1 xxxxx 4 left shift result decrement result exponent e g 0 001xx right shift result increment result exponent e g 101 1xx continue until MSB of data is 1 NOTE Hidden bit in IEEE Standard 5 for multiply doubly biased exponent must be corrected Xe 7 Ye 3 Excess 8 7 8 15 Xe 1111 3 8 5 Ye 0101 4 8 8 20 10100 extra subtraction step of the bias amount 1 xxxxx 1 xxxxx 0 001xxxxx 0 01xxxxx 1x xxxxy 1 xxxxxyyy 1x xxxxyyy post normalization pre normalization pre and post Guard Digits digits to the right of the first p digits of significand to guard against loss of digits can later be shifted left into first P places during normalization Addition carry out shifted in Subtraction borrow digit and guard 6 if result is 0 mantissa may need to zero exponent by special step 9 22 01 UCB Fall 2001 CS152 Kubiatowicz Lec7 9 Multiplication carry and guard Division requires guard 9 22 01 Rounding Digits UCB Fall 2001 CS152 Kubiatowicz Lec7 10 Sticky Bit normalized result but some non zero digits to the right of the significand the number should be rounded 2 bias 0 2 1 69 1 6900 10 0 0 7 45 0745 10 2 bias 0 2 1 62 1 6155 10 2 bias one round digit must be carried to the right of the guard digit so that after a normalizing left shift the result can be rounded according to the value of the round digit E g B 10 p 3 Additional bit to the right of the round digit to better fine tune rounding d0 d1 d2 d3 dp 1 0 0 0 0 0 0 X X XX S XX S d0 d1 d2 d3 dp 1 0 0 0 0 0 0 X X XX 0 XX0 Sticky bit set to 1 if any 1 bits fall off the end of the round digit d0 d1 d2 d3 dp 1 0 0 0 0 0 0 X X XX 1 generates a borrow Rounding Summary IEEE Standard four rounding modes round to nearest even default round towards plus infinity round towards minus infinity round towards 0 round to nearest round digit B 2 then truncate B 2 then round up add 1 to ULP unit in last place B 2 then round to nearest even digit it can be shown that this strategy minimizes the mean error introduced by rounding 9 22 01 UCB Fall 2001 CS152 Kubiatowicz Lec7 11 Radix 2 minimizes wobble in precision Normal operations in require one carry borrow bit one guard digit One round digit needed for correct rounding Sticky bit needed when round digit is …
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