CS 152 Computer Architecture and Engineering Lecture 5 Timing 2005 2 1 John Lazzaro www cs berkeley edu lazzaro TAs Ted Hong and David Marquardt www inst eecs berkeley edu cs152 CS 152 L5 Timing UC Regents Spring 2005 UCB Last Time Making a Test Plan Top down testing complete processor testing processor testing with self checks multi unit testing Which testing types are good for each epoch Epoch 1 unit testing early multi unit testing later Epoch 2 Epoch 3 Epoch 4 processor testing with self checks processor testing with self checks complete processor testing multi unit testing multi unit testing unit testing unit testing verification processor testing with self checks diagnostics diagnostics diagnostics Time unit testing Bottom up testing processor assembly complete correctly executes single instructions correctly executes short programs New this year test benches checked off early CS 152 L5 Timing UC Regents Spring 2005 UCB Last Time Works in ModelSim but Top down testing Idea get confidence in going to board earlier complete processor testing processor testing with self checks multi unit testing Epoch 1 Epoch 2 Epoch 3 Epoch 4 ModelSim ModelSim ModelSim ModelSim 80 80 80 Xilinx Xilinx Xilinx Xilinx 20 20 20 80 20 Time unit testing processor assembly complete Bottom up testing correctly executes single instructions correctly executes short programs Also catch Synplicity warnings and errors earlier CS 152 L5 Timing UC Regents Spring 2005 UCB Today Determine minimum clock period 32 PC Equal Instr Mem 32 32 32 D Q 32 Addr Combinational Logic Data 32 Step 1a The MIPS lite Subset for today 32 0x4 PCSrc 31 ADD and SUB 26 op E addU x rd rs rt t rd rs 32 rt subU 6 bits 31 Clk 16 21 rs 5 bits rt 5 bits 26 21 16 op 6 bits 31 26 LOAD and STORE Word op lw rt rs imm16 6 bits rs 5 bits 21 rs 5 bits rt 5 bits 16 rt 5 bits e n OR Immediate d ori rt rs imm16 sw rt rs imm16 5 BRANCH beq rs rt imm16 5 5 CS 152 L06 Single Cycle 1 6 RegDest 11 rd 5 bits 6 shamt 5 bits immediate 16 bits ws 32 wd 32 WE ALUctr 0 op 16 bits 32 Data Memory UC Regents Fall 2004 UCB 32 ExtOp A L U 32 Addr Equal 32 Dout Din Ext RegWr CS 152 L5 Timing Control Lines 0 immediate 16 bits 32 immediate rd2 funct 6 bits 0 RegFile 26 21 16 rs1 op rs rt 6 bits 5 bits 5 bits rd1 rs2 31 0 32 WE MemToReg ALUsrc MemWr UC Regents Spring 2005 UCB Today s Lecture Timing Analysis Combinational logic delay Clocked logic and delay Xilinx and delay CS 152 L5 Timing UC Regents Spring 2005 UCB View from 10 000 Feet CS 152 L5 Timing UC Regents Spring 2005 UCB Architects draw blocks IEEE JOURNAL OF SOLID STATE CIRCUITS VOL 36 NO 11 NOVEMBER 2001 Circuit designers draw transistors 0 4 5678 9 8 8 9 0 1 2 3 4 5678 9 8 8 9 4 4 4 4 8 8 8 8 8 1 6 2 88 8 1 A9 9 A1 B 8 1 8 78 7 8 8 C0B 8 8 6 1 A 8 8 Logic is where they meet Fig 2 Microprocessor pipeline organization L5 Timing shown in Fig CS2 152 where the state boundaries are indicated by 012 34 5 UC Regents Spring 2005 UCB Architects reach logic top down Rst Change Next State Combinational Logic R next R wire next G G next Y Y next R next Y next G assign next R rst 1 b1 change Y R assign next Y rst 1 b0 change G Y assign next G rst 1 b0 change R G Using schematics and behavioral Verilog CS 152 L5 Timing UC Regents Spring 2005 UCB EEs reach logicCMOS bottom up Basic Components Logic Gates NOR Gate NAND Gate A B Out A 0 0 1 1 B Out 0 1 1 1 0 1 1 0 Out A B Vdd Out B A 1 28 04 CS 152 L5 Timing A 0 0 1 1 B Out 0 1 1 0 0 0 1 0 SmallOutnumber B of high performance logic circuits Out A B A Vdd For some definition A of small and B high performance Out Can you build a processor CS152 Kubiatowicz UCB Spring 2004 entirely out of NAND Lec3 33 gates UC Regents Spring 2005 UCB Intermediate Specification Logic Synthesis often bridges the gap Final Architectural Description refinement increasing level of detail assign next R rst 1 b1 change Y R assign next Y rst 1 b0 change G Y assign next G rst 1 b0 change R G Intermediate Specification of Implementation refinement increasing level of detail Final Internal Specification Physical Implementation Logic Components Logic Components UCB Spring 2004 Still in the highest performance Elements of the design zoo Wires Carry signals from one point designs human designers do some Combinational Logic Like function logic circuits and Basic Combinational Elements DeMorgan Equivalence layout by hand ic Components pring 2004 1 28 04 CS152 Kubiatowicz Lec3 5 CS152 Kubiatowicz Lec3 5 1 28 04 CS152 Kubiatowicz Lec3 6 Single CS152 Kubiatowicz Lec3 6 UCB Spring 2004 1 28 04 UCB Spring 2004 bit no size label or multi bit bus siz 8 Data goes in Results come out after some CS152 Kubiatowicz Lec3 6 UCB Spring 2004 Combinational Logic Basic Combinational Elements DeMorgan Equivalence oo oint to another one point to another Wire s size label ti bit bus size label Out In Out In 8 8 on evaluation nal Elements DeMorgan Equivalence function evaluation ome propagation delay t after some propagation delay Inverter ut In Out nal 0 1 Out In In Out 1 0 1 0 A B Wire In Out In Out 0 0 0 01 1 1 1 A B Out Out0 0 1 1 00 10 01 11 Out Out A BA AB BA B 01 11 01 10 1 1 1 0 Out Out 11 In Out In Out 1 Flip Flops Storage Elements 0 1 0 01 After a clock edge input copied to output 1 0 NOR Gate NOR GateA B Out A B Out A A B B DeMorgan s DeMorgan s Theorem Theorem A Out B Out A BA AB B In Out In Out In NAND Gate NAND Gate A B Out A B Out nts put d to output NOR Gate Out s value A B Out 1 is level CS 152 L5 Timing 0 0 ment that is level triggered at triggered 1 A Out In Inverter Inverter OutOut 0 00 0 01 1 10 1 11 0 1 0 1 Otherwise the flip flop holds its value Also a Latch is a storage element that is 11 00 00 00 1 28 04 D Q D 8 Q 8 UCB Spring 2004 OutOut A A B B B BA A Out A AB B A A B BOut UC Regents Spring 2005 UCB A Logic Circuit Primer CS 152 L5 Timing UC Regents Spring …
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