CS152 Computer Architecture and Engineering Lecture 8 Multicycle Design and Microcode 2004 09 23 John Lazzaro www cs berkeley edu lazzaro Dave Patterson www cs berkeley edu patterson www inst eecs berkeley edu cs152 CS 152 L09 Multicycle 1 Fall 2004 UC Regents Review Single cycle datapath CPI 1 CCT long 5 steps to design a processor 1 Analyze instruction set datapath requirements 2 Select set of datapath components establish clock methodology 3 Assemble datapath meeting the requirements 4 Analyze implementation of each instruction to determine setting of control points that effects the register transfer 5 Assemble the control logic Processor Control is the hard part Control MIPS makes control easier Datapath Instructions same size Source registers always in same place Input Memory Output Immediates same size location Operations always on registers immediates CS 152 L09 Multicycle 2 Fall 2004 UC Regents What s wrong with our CPI 1 processor Arithmetic Logical PC Inst Memory Reg File mux ALU Inst Memory Reg File mux ALU Data Mem mux ALU Data Mem mux setup Load PC mux setup Critical Path Store PC Inst Memory Reg File Inst Memory Reg File Branch PC cmp mux Long Cycle Time All instructions take as much time as the slowest Real memory slower than idealized memory Duplicate Resources CS 152 L09 Multicycle 3 Fall 2004 UC Regents Memory Access Time Physics fast memories are small large memories are slow Storage Array selected word line storage cell address bit line address decoder sense amps Processor L2 Cache 1 time period 2 3 time periods CS 152 L09 Multicycle 4 mem bus Cache proc bus Use a hierarchy of memories memory 20 50 time periods Fall 2004 UC Regents Reducing Cycle Time Cut combinational dependency graph and insert register latch Do same work in two fast cycles rather than one slow one May be able to short circuit path and remove some components for storage element some instructions storage element Acyclic Combinational Logic A Acyclic Combinational Logic storage element Acyclic Combinational Logic B storage element storage element CS 152 L09 Multicycle 5 Fall 2004 UC Regents Limits on Cycle Time new view of datapath Next address logic PC branch PC offset PC 4 Instruction Fetch InstructionReg Mem PC Register Access A R rs ALU operation CS 152 L09 Multicycle 6 Result Store MemWr RegWr RegDst Data Mem Reg File MemWr Mem Access Exec ALUctr ALUSrc ExtOp Operand Fetch Instruction Fetch PC Next PC nPC sel R A B MemRd Control Fall 2004 UC Regents Partitioning the CPI 1 Datapath 1 Result Store Place so that balances length of clock cycle 2 MemWr RegWr RegDst Data Mem Reg File MemWr MemRd ALUctr ExtOp ALUSrc Exec Mem Access Operand Fetch Instruction Fetch PC Next PC nPC sel Equal Add registers between smallest steps Logic delays about the same between registers Place to save information needed later in instruction execution CS 152 L09 Multicycle 7 Fall 2004 UC Regents CS 152 L09 Multicycle 8 B Ext ALU A Reg File S Result Store Reg File Mem Access IR RegWr RegDst MemToReg MemWr MemRd ALUctr ALUSrc ExtOp Equal nPC sel E Data Mem Operand Fetch Instruction Fetch PC Next PC Example Multicycle Datapath M Critical Path Fall 2004 UC Regents Recall Step by step Processor Design Step 1 ISA Logical Register Transfers Step 2 Components of the Datapath Step 3 RTL Components Datapath Step 4 Datapath Logical RTs Physical RTs Step 5 Physical RTs Control CS 152 L09 Multicycle 9 Fall 2004 UC Regents inst Logical Register Transfers ADDU R rd R rs R rt PC PC 4 Physical Register Transfers inst Physical Register Transfers IR MEM pc Time ADDU A R rs B R rt S A B R rd S PC PC 4 S M Data Mem B Reg File A Mem Access Reg File IR Inst Mem PC Next PC E Exec Step 4 R rtype add sub Logical Register Transfer CS 152 L09 Multicycle 10 Fall 2004 UC Regents Administrivia Working on Homework 2 Single cycle simulation demo on Friday add to your calendar Midterm 1 on Tuesday Oct 12 5 30 8 30pm 306 Soda CS 152 L09 Multicycle 11 Fall 2004 UC Regents Step 4 Logical immed Logical Register Transfer inst Logical Register Transfers ORI R rt R rs ZExt Im16 PC PC 4 Physical Register Transfers inst Physical Register Transfers IR MEM pc Time ORI A R rs B R rt S A ZExt Im16 R rt S PC PC 4 Reg File M Data Mem B S Mem Access A Exec Reg File IR Inst Mem PC Next PC E CS 152 L09 Multicycle 12 Fall 2004 UC Regents Step 4 Logical Register Transfer Load inst Logical Register Transfers LW R rt MEM R rs SExt Im16 PC PC 4 Physical Register Transfers inst Physical Register Transfers IR MEM pc LW A R rs B R rt Time S A SExt Im16 M MEM S R rd M PC PC 4 Reg File M Data Mem B S Mem Access A Exec Reg File IR Inst Mem PC Next PC E CS 152 L09 Multicycle 13 Fall 2004 UC Regents Step 4 Logical Register Transfer Store inst Logical Register Transfers SW MEM R rs SExt Im16 R rt PC PC 4 Physical Register Transfers inst Physical Register Transfers IR MEM pc Time SW A R rs B R rt S A SExt Im16 MEM S B PC PC 4 Reg File M Data Mem B S Mem Access A Exec Reg File IR Inst Mem PC Next PC E CS 152 L09 Multicycle 14 Fall 2004 UC Regents Step 4 Logical Register Transfer Branch inst Logical Register Transfers BEQ if R rs R rt then PC PC 4 SExt Im16 2 b00 else PC PC 4 Physical Register Transfers inst Physical Register Transfers Time IR MEM pc BEQ E R rs R rt if E PC PC 4 else PC PC 4 SExt Im16 2 b0 Reg File M Data Mem B S Mem Access A Exec Reg File IR Inst Mem PC Next PC E CS 152 L09 Multicycle 15 Fall 2004 UC Regents Alternative datapath book Multiple Cycle Datapath Minimizes Hardware 1 memory 1 adder PCWr PCWrCond PCSrc BrWr Zero IorD MemWr IRWr RegDst ALUSelA RegWr Mux 32 PC WrAdr 32 Din 32 Dout Rb 32 Rd 1 Imm 32 1 32 4 0 Rw 32 busW 1 32 busB 32 1 2 Mux 0 2 3 32 ALU Control Extend 16 ExtOp CS 152 L09 Multicycle 16 Reg File 5 0 Rt busA Zero ALU Out 1 Rt Mux Ideal Memory Ra 5 32 ALU 32 Instruction Reg Mux RAdr Mux Rs 0 32 0 0 32 Target 1 32 MemtoReg ALUOp ALUSelB Fall 2004 UC Regents Our Control StateModel specifies control points for Register Transfer Transfer occurs upon exiting state same clock edge inputs conditions Next State Logic Control State State X Register Transfer Control Points Depends on Input Output Logic outputs control points CS 152 L09 Multicycle 17 Fall 2004 UC Regents Step 4 Control Spec for multicycle proc instruction fetch IR MEM PC Finite State Diagram decode operand fetch A R rs B R rt SW BEQ …
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