PowerPoint PresentationReviewWhat’s wrong with our CPI=1 processor?Memory Access TimeReducing Cycle TimeLimits on Cycle Time (new view of datapath)Partitioning the CPI=1 DatapathExample Multicycle DatapathRecall: Step-by-step Processor DesignStep 4: R-rtype (add, sub, . . .)AdministriviaStep 4: Logical immedStep 4 : LoadStep 4 : StoreStep 4 : BranchAlternative datapath (book): Multiple Cycle DatapathOur Control ModelStep 4 Control Spec for multicycle procTraditional FSM ControllerStep 5 (datapath + state diagram control)Mapping Register Transfers to Control PointsAssigning States(Mostly) Detailed Control Specs (missing0)Instruction Set and Control OptionsController DesignOur MicrosequencerAdding the Dispatch ROMMicroprogrammingSlide 29“Macroinstruction” InterpretationDesigning a “Microinstruction Set”Again: Alternative multicycle datapath (book)1&2) Start with list of control signals, grouped into fields3&4) Microinstruction Format: unencoded vs. encoded fields5) Legend of Fields and Symbolic NamesQuick check: what do these fieldnames mean?Specific Sequencer from beforeMicroprogram it yourself!Overview of ControlMicroprogramming Pros and ConsLegacy Software and MicroprogrammingThought: Microprogramming one inspiration for RISCSummary (1 of 3)Summary (cont’d) (2 of 3)Summary (3 of 3)Where to get more information?CS 152 L09 Multicycle (1)Fall 2004 © UC RegentsCS152 – Computer Architecture andEngineeringLecture 8 – Multicycle Design and Microcode2004-09-23John Lazzaro(www.cs.berkeley.edu/~lazzaro)Dave Patterson (www.cs.berkeley.edu/~patterson)www-inst.eecs.berkeley.edu/~cs152/CS 152 L09 Multicycle (2)Fall 2004 © UC Regents°Single cycle datapath => CPI=1, CCT => long°5 steps to design a processor•1. Analyze instruction set => datapath requirements•2. Select set of datapath components & establish clock methodology•3. Assemble datapath meeting the requirements•4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.•5. Assemble the control logic°Control is the hard part°MIPS makes control easier•Instructions same size•Source registers always in same place•Immediates same size, location•Operations always on registers/immediatesReviewControlDatapathMemoryProcessorInputOutputCS 152 L09 Multicycle (3)Fall 2004 © UC RegentsWhat’s wrong with our CPI=1 processor?•Long Cycle Time–All instructions take as much time as the slowest–Real memory slower than idealized memory•Duplicate ResourcesPC Inst MemorymuxALU Data MemmuxPC Reg FileInst MemorymuxALUmuxPC Inst MemorymuxALU Data MemPC Inst Memory cmpmuxReg FileReg FileReg FileArithmetic & LogicalLoadStoreBranchCritical PathsetupsetupCS 152 L09 Multicycle (4)Fall 2004 © UC RegentsMemory Access Time•Physics => fast memories are small (large memories are slow)•=> Use a hierarchy of memoriesStorage Arrayselected word lineaddressstorage cellbit linesense ampsaddressdecoderCacheProcessor1 time-periodproc. busL2Cachemem. bus2-3 time-periods20 - 50 time-periodsmemoryCS 152 L09 Multicycle (5)Fall 2004 © UC RegentsReducing Cycle Time•Cut combinational dependency graph and insert register / latch•Do same work in two fast cycles, rather than one slow one•May be able to short-circuit path and remove some components for some instructions!storage elementAcyclic CombinationalLogicstorage elementstorage elementAcyclic CombinationalLogic (A)storage elementstorage elementAcyclic CombinationalLogic (B)CS 152 L09 Multicycle (6)Fall 2004 © UC RegentsLimits on Cycle Time (new view of datapath)•Next address logic–PC <= branch ? PC + offset : PC + 4•Instruction Fetch–InstructionReg <= Mem[PC]•Register Access–A <= R[rs]•ALU operation–R <= A + BPCNext PCOperandFetchExecReg. FileMemAccessDataMemInstructionFetchResult StoreALUctrRegDstALUSrcExtOpMemWrnPC_selRegWrMemWrMemRdControlCS 152 L09 Multicycle (7)Fall 2004 © UC RegentsPartitioning the CPI=1 Datapath•Add registers between smallest steps1. Place so that balances length of clock cycle•Logic delays about the same between registers2. Place to save information needed later in instruction executionPCNext PCOperandFetchExecReg. FileMemAccessDataMemInstructionFetchResult StoreALUctrRegDstALUSrcExtOpMemWrnPC_selRegWrMemWrMemRdEqualCS 152 L09 Multicycle (8)Fall 2004 © UC RegentsExample Multicycle Datapath•Critical Path ?PCNext PCOperandFetchInstructionFetchnPC_selIRRegFileExtALUReg. FileMemAccessDataMemResult StoreRegDstRegWrMemWrMemRdSMMemToRegEqualALUctrALUSrcExtOpABECS 152 L09 Multicycle (9)Fall 2004 © UC RegentsRecall: Step-by-step Processor DesignStep 1: ISA => Logical Register TransfersStep 2: Components of the DatapathStep 3: RTL + Components => DatapathStep 4: Datapath + Logical RTs => Physical RTsStep 5: Physical RTs => ControlCS 152 L09 Multicycle (10)Fall 2004 © UC RegentsStep 4: R-rtype (add, sub, . . .)•Logical Register Transfer•Physical Register Transfersinst Logical Register TransfersADDU R[rd] <= R[rs] + R[rt]; PC <= PC + 4inst Physical Register TransfersIR <= MEM[pc]ADDU A<= R[rs]; B <= R[rt]S <= A + BR[rd] <= S; PC <= PC + 4ExecReg. FileMemAccessDataMemSMRegFilePCNext PCIRInst. MemTimeABECS 152 L09 Multicycle (11)Fall 2004 © UC RegentsAdministrivia•Working on Homework #2•Single cycle simulation demo on Friday•(add to your calendarMidterm 1 on Tuesday Oct 12 5:30 - 8:30pm 306 Soda)CS 152 L09 Multicycle (12)Fall 2004 © UC RegentsStep 4: Logical immed•Logical Register Transfer•Physical Register Transfersinst Logical Register TransfersORI R[rt] <= R[rs] | ZExt(Im16); PC <= PC + 4inst Physical Register TransfersIR <= MEM[pc]ORI A<= R[rs]; B <= R[rt]S <= A | ZExt(Im16)R[rt] <= S; PC <= PC + 4ExecReg. FileMemAccessDataMemSMRegFilePCNext PCIRInst. MemTimeABECS 152 L09 Multicycle (13)Fall 2004 © UC RegentsStep 4 : Load•Logical Register Transfer•Physical Register Transfersinst Logical Register TransfersLW R[rt] <= MEM[R[rs] + SExt(Im16)]; PC <= PC + 4inst Physical Register TransfersIR <= MEM[pc]LW A<= R[rs]; B <= R[rt]S <= A + SExt(Im16)M <= MEM[S]R[rd] <= M; PC <= PC + 4ExecReg. FileMemAccessDataMemSMRegFilePCNext PCIRInst. MemABETimeCS 152 L09 Multicycle (14)Fall 2004 © UC RegentsStep 4 : Store•Logical Register Transfer•Physical Register Transfersinst Logical Register TransfersSW MEM[R[rs] + SExt(Im16)] <= R[rt];PC <= PC + 4inst Physical Register TransfersIR <= MEM[pc]SW A<= R[rs]; B <= R[rt]S <= A +
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