CS152 Computer Architecture and Engineering Lecture 5 High-Level Design FPGAs/Vertex-E ChipsetReview: Elements of the Design ProcessReview: ALU DesignReview: Carry Look Ahead (Design trick: peek)Review: Design Trick: Guess (or “Precompute”)Why should you keep a design notebook?Why do we keep it on-line?How should you do it?On-line Notebook Example1st page of On-line notebook (Index + Wed. 9/6/95)2nd page of On-line notebook (Thursday 9/7/95)3rd page of On-line notebook (Monday 9/11/95)4th page of On-line notebook (9/11/95 contd)5th page of On-line notebook (9/11/95 contd)Representation LanguagesSimulation Before ConstructionLevels of DescriptionNetlistDesign FlowSlide 20Slide 21Slide 22Slide 23Design EntryHigh Level Design Languages (HDLs)Verilog HistoryExample: Structural XOR (xor built-in, but..)Example: Behavioral XOR in VerilogVerilog big idea: Time in codeDelay SpecificationsTime ExampleTime, variable update, and monitorSequential LogicVerilog: replication, hierarchyExample: Replicated XOR in VerilogBasic Example: 2-to1 mux in Structural Form2-1 Mux in Dataflow Form2-to-1 mux Behavioral descriptionCombining modules: Hierarchy & Bit VectorsBehavioral 4-to1 muxBehavioral with Bit VectorsTesting: Make sure that things workMonitor Modules: Passthrough testingTestbench: Applying Directed VectorsTestbench: Randomized Vector TestingMore Verilog HelpPowerPoint PresentationFPGA VariationsUser ProgrammabilityIdealized FPGA Logic Block4-LUT ImplementationLUT as general logic gateMore functionality for “free”?Slide 54Slide 55Slide 56Slide 57How Program: FPGA Generic Design FlowExample Partition, Placement, and RouteSlide 60Virtex-E Configurable Logic Block (CLB)Slide 62Details of Virtex-E SliceSlide 64Xilinx Virtex-E Chip FloorplanSlide 66Slide 67Slide 68Slide 69Virtex-E Family of PartsSummary ISummary: Xilinx FPGAsCS152Computer Architecture and Engineering Lecture 5 High-Level DesignFPGAs/Vertex-E ChipsetFebruary 9, 2004John Kubiatowicz (www.cs.berkeley.edu/~kubitron)lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/2/9/034 ©UCB Spring 2004CS152 / Kubiatowicz Lec5.2Review: Elements of the Design Process°Divide and Conquer (e.g., ALU)•Formulate a solution in terms of simpler components.•Design each of the components (subproblems)°Generate and Test (e.g., ALU)•Given a collection of building blocks, look for ways of putting them together that meets requirement°Successive Refinement (e.g., multiplier, divider)•Solve "most" of the problem (i.e., ignore some constraints or special cases), examine and correct shortcomings.°Formulate High-Level Alternatives (e.g., shifter)•Articulate many strategies to "keep in mind" while pursuing any one approach.°Work on the Things you Know How to Do•The unknown will become “obvious” as you make progress.2/9/034 ©UCB Spring 2004CS152 / Kubiatowicz Lec5.3Review: ALU Design°Bit-slice plus extra on the two ends°Overflow means number too large for the representation°Carry-look ahead and other adder tricksAMS32324OvflwALU0a0 b0cincos0ALU31a31 b31cincos31B 32C/L toproduceselect,comp,c-insigned-arithand cin xor co2/9/034 ©UCB Spring 2004CS152 / Kubiatowicz Lec5.4Review: Carry Look Ahead (Design trick: peek)A B C-out0 0 0 “kill”0 1 C-in “propagate”1 0 C-in “propagate”1 1 1 “generate”G = A and BP = A xor BA0B0A1B1A2B2A3B3SSSSGPGPGPGPC0 = CinC1 = G0 + C0 - P0C2 = G1 + G0 -P1 + C0 - P0 - P1C3 = G2 + G1 -P2 + G0 - P1 - P2 + C0 - P0 - P1 - P2GC4 = . . .P2/9/034 ©UCB Spring 2004CS152 / Kubiatowicz Lec5.5Review: Design Trick: Guess (or “Precompute”)n-bit adder n-bit adderCP(2n) = 2*CP(n)n-bit addern-bit addern-bit adder10CoutCP(2n) = CP(n) + CP(mux)Carry-select adder2/9/034 ©UCB Spring 2004CS152 / Kubiatowicz Lec5.6Why should you keep a design notebook?°Keep track of the design decisions and the reasons behind them•Otherwise, it will be hard to debug and/or refine the design•Write it down so that can remember in long project: 2 weeks ->2 yrs•Others can review notebook to see what happened°Record insights you have on certain aspect of the design as they come up°Record of the different design & debug experiments•Memory can fail when very tired°Industry practice: learn from others mistakes2/9/034 ©UCB Spring 2004CS152 / Kubiatowicz Lec5.7Why do we keep it on-line?°You need to force yourself to take notes•Open a window and leave an editor running while you work1) Acts as reminder to take notes2) Makes it easy to take notes•1) + 2) => will actually do it°Take advantage of the window system’s “cut and paste” features°It is much easier to read your typing than your writing°Also, paper log books have problems•Limited capacity => end up with many books•May not have right book with you at time vs. networked screens•Can use computer to search files/index files to find what looking for2/9/034 ©UCB Spring 2004CS152 / Kubiatowicz Lec5.8How should you do it?°Keep it simple•DON’T make it so elaborate that you won’t use (fonts, layout, ...)°Separate the entries by dates•type “date” command in another window and cut&paste°Start day with problems going to work on today°Record output of simulation into log with cut&paste; add date•May help sort out which version of simulation did what°Record key email with cut&paste°Record of what works & doesn’t helps team decide what went wrong after you left°Index: write a one-line summary of what you did at end of each day2/9/034 ©UCB Spring 2004CS152 / Kubiatowicz Lec5.9On-line Notebook Example°Refer to the handout “Example of On-Line Log Book” on cs 152 handouts page2/9/034 ©UCB Spring 2004CS152 / Kubiatowicz Lec5.101st page of On-line notebook (Index + Wed. 9/6/95)* Index ==============================================================Wed Sep 6 00:47:28 PDT 1995 - Created the 32-bit comparator componentThu Sep 7 14:02:21 PDT 1995 - Tested the comparatorMon Sep 11 12:01:45 PDT 1995 - Investigated bug found by Bart in comp32 and fixed it+ ====================================================================Wed Sep 6 00:47:28 PDT 1995 Goal: Layout the schematic for a 32-bit comparator I've layed out the schemtatics and made a symbol for the comparator. I named it comp32. The files are ~/wv/proj1/sch/comp32.sch ~/wv/proj1/sch/comp32.symWed Sep 6 02:29:22 PDT 1995- ====================================================================• Add 1 line index at front of log
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