CS152 Computer Architecture and Engineering Lecture 5 High Level Design FPGAs Vertex E Chipset February 9 2004 John Kubiatowicz www cs berkeley edu kubitron lecture slides http www inst eecs berkeley edu cs152 Review Elements of the Design Process Divide and Conquer e g ALU Formulate a solution in terms of simpler components Design each of the components subproblems Generate and Test e g ALU Given a collection of building blocks look for ways of putting them together that meets requirement Successive Refinement e g multiplier divider Solve most of the problem i e ignore some constraints or special cases examine and correct shortcomings Formulate High Level Alternatives e g shifter Articulate many strategies to keep in mind while pursuing any one approach Work on the Things you Know How to Do The unknown will become obvious as you make progress 2 9 034 UCB Spring 2004 CS152 Kubiatowicz Review ALU Design Bit slice plus extra on the two ends Overflow means number too large for the representation Carry look ahead and other adder tricks A 32 B 32 signed arith and cin xor co a31 a0 b31 ALU0 co cin s0 ALU31 co cin s31 Ovflw 2 9 034 b0 S 32 UCB Spring 2004 4 M C L to produce select comp c in CS152 Kubiatowicz Review Carry Look Ahead Design trick peek C0 Cin A0 B0 G P A 0 0 1 1 S C1 G0 C0 P0 A1 B1 G P S B 0 1 0 1 C out 0 C in C in 1 kill propagate propagate generate G A and B P A xor B C2 G1 G0 P1 C0 P0 P1 A2 B2 G P S C3 G2 G1 P2 G0 P1 P2 C0 P0 P1 P2 A3 B3 G P S G P C4 2 9 034 UCB Spring 2004 CS152 Kubiatowicz Review Design Trick Guess or Precompute CP 2n 2 CP n n bit adder n bit adder CP 2n CP n CP mux n bit adder 1 n bit adder n bit adder Carry select adder Cout 2 9 034 0 UCB Spring 2004 CS152 Kubiatowicz Why should you keep a design notebook Keep track of the design decisions and the reasons behind them Otherwise it will be hard to debug and or refine the design Write it down so that can remember in long project 2 weeks 2 yrs Others can review notebook to see what happened Record insights you have on certain aspect of the design as they come up Record of the different design debug experiments Memory can fail when very tired Industry practice learn from others mistakes 2 9 034 UCB Spring 2004 CS152 Kubiatowicz Why do we keep it online You need to force yourself to take notes Open a window and leave an editor running while you work 1 Acts as reminder to take notes 2 Makes it easy to take notes 1 2 will actually do it Take advantage of the window system s cut and paste features It is much easier to read your typing than your writing Also paper log books have problems Limited capacity end up with many books May not have right book with you at time vs networked screens Can use computer to search files index files to find what looking for 2 9 034 UCB Spring 2004 CS152 Kubiatowicz How should you do it Keep it simple DON T make it so elaborate that you won t use fonts layout Separate the entries by dates type date command in another window and cut paste Start day with problems going to work on today Record output of simulation into log with cut paste add date May help sort out which version of simulation did what Record key email with cut paste Record of what works doesn t helps team decide what went wrong after you left Index write a one line summary of what you did at end of each day 2 9 034 UCB Spring 2004 CS152 Kubiatowicz On line Notebook Example Refer to the handout Example of On Line Log Book on cs 152 handouts page 2 9 034 UCB Spring 2004 CS152 Kubiatowicz 1st page of On line notebook Index Wed 9 6 95 Index Wed Sep 6 00 47 28 PDT 1995 Created the 32 bit comparator component Thu Sep 7 14 02 21 PDT 1995 Tested the comparator Mon Sep 11 12 01 45 PDT 1995 Investigated bug found by Bart in comp32 and fixed it Wed Sep 6 00 47 28 PDT 1995 Goal Layout the schematic for a 32 bit comparator I ve layed out the schemtatics and made a symbol for the comparator I named it comp32 The files are wv proj1 sch comp32 sch wv proj1 sch comp32 sym Wed Sep 6 02 29 22 PDT 1995 Add 1 line index at front of log file at end of each session date summary Start with date time of day goal Make comments during day summary of work End with date time of day and add 1 line summary at front of file 2 9 034 UCB Spring 2004 CS152 Kubiatowicz 2nd page of On line notebook Thursday 9 7 95 Thu Sep 7 14 02 21 PDT 1995 Goal Test the comparator component I ve written a command file to test comp32 I ve placed it in wv proj1 diagnostics comp32 cmd I ran the command file in viewsim and it looks like the comparator is working fine I saved the output into a log file called wv proj1 diagnostics comp32 log Notified the rest of the group that the comparator is done Thu Sep 7 16 15 32 PDT 1995 2 9 034 UCB Spring 2004 CS152 Kubiatowicz 3rd page of On line notebook Monday 9 11 95 2 9 034 UCB Spring 2004 CS152 Kubiatowicz 4th page of On line notebook 9 11 95 contd 2 9 034 UCB Spring 2004 CS152 Kubiatowicz 5th page of On line notebook 9 11 95 contd Perhaps later critical path changes what was idea to make compartor faster Check log book 2 9 034 UCB Spring 2004 CS152 Kubiatowicz Representation Languages Hardware Representation Languages Block Diagrams FUs Registers Dataflows Register Transfer Diagrams Choice of busses to connect FUs Regs Flowcharts Two different ways to describe sequencing microoperations State Diagrams Fifth Representation Language Hardware Description Languages hw modules described like programs with i o ports internal state parallel execution of assignment statements E G ISP VHDL Verilog Descriptions in these languages can be used as input to simulation systems software breadboard synthesis systems generate hw from high level description To Design is to Represent 2 9 034 UCB Spring 2004 CS152 Kubiatowicz Simulation Before Construction Physical Breadboarding discrete components lower scale integration preceeds actual construction of prototype verify initial design concept No longer possible as designs reach higher levels of integration Simulation Before Construction high level constructs implies faster to construct play what if more easily limited performance accuracy however 2 9 034 UCB Spring 2004 CS152 Kubiatowicz Levels of Description Architectural Simulation models programmer s view at a high level written in your favorite programming language Functional Behavioral Dataflow more …
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