CS 152 Computer Architecture and Engineering Lecture 20 Buses Disks and RAID 2005 11 8 John Lazzaro www cs berkeley edu lazzaro TAs David Marquardt and Udam Saini www inst eecs berkeley edu cs152 CS 152 L20 Buses Disks and RAID UC Regents Fall 2005 UCB Last Time Multithreading Multiple Cores CS 152 L20 Buses Disks and RAID 1 1 Threads Threads on on two two cores cores that that use use shared shared libraries libraries conserve conserve L2 L2 memory memory 2 2 Threads Threads on on two two cores cores share share memory memory via via L2 L2 cache cache operations operations Much Much faster faster than than UC Regents Fall 2005 UCB Today Buses Disks and RAID Buses Shared physical wires that act to communicate signals between several devices often peripherals Buses Buses let let computers computers be be expandable expandable add add more more memory memory a a better better graphics graphics card card a a webcam webcam etc etc Disks Store bits as the orientation of miniature bar magnets on a rotating platter A mechanical device slow and prone to failure CS 152 L20 Buses Disks and RAID UC Regents Fall 2005 UCB Properties of bus structures Control lines Controls transactions signals what is on data lines Data lines Carries information across the interface Buses are an abstraction for communication helps designers CS 152 L20 Buses Disks and RAID UC Regents Fall 2005 UCB Buses are defined in layers Example DIMM DRAM bus The name of every wire is defined in a standards document Transaction Protocols Signal Timing on Wires Wires Electrical Properties Mechanical Properties CS 152 L20 Buses Disks and RAID JEDEC Joint Electron Device Engineering Council Makes the DRAM UC Regents Fall 2005 UCB Lower levels of DRAM bus specification Transaction Protocols Signal Timing on Wires Wires Electrical Properties Mechanical Properties Ideally DIMMs made by any manufacturer should fit into any compliant socket and work CS 152 L20 Buses Disks and RAID UC Regents Fall 2005 UCB Upper levels of DRAM bus specification Collaboration between DRAM manufacturers Samsung Micron and DRAM users Intel Cisco Transaction Protocols Signal Timing on Wires Wires Electrical Properties Mechanical Properties CS 152 L20 Buses Disks and RAID UC Regents Fall 2005 UCB Bus wires shared between many DIMMS Apple Xserve G5 has 8 DIMM slots to support 8GB DIMMs respond to transaction requests Since memory controller is only bus master and there are a small number of DIMM slots bus sharing is easy use dedicated wires to each slot Memory controller is the only bus master it can start transactions on the bus but the DIMMs CS 152 L20 Buses Disks and RAID UC Regents Fall 2005 UCB Buses pros and cons Low cost One set of wires from memory controller can support up to 8 DIMMs Latency of bus increases with length of wires needed to reach all 8 DIMM sockets and the loading of 8 DIMMs Must design for worst case 8 DIMMs even if only 1 DIMM is present Shared wires limit maximum bandwidth from memory If memory controller had 8 sets of dedicated wires one per DIMM memory CS 152 L20 Buses Disks and RAID UC Regents Fall 2005 UCB Buses turn a CPU into a product Case Study Mac Mini CS 152 L20 Buses Disks and RAID UC Regents Fall 2005 UCB Constraints Size low price 499 USD Size Size fixed fixed by by the the form form factor factor physical physical size size of of desktop desktop DIMMS DIMMS Laptop Laptop DRAM DRAM is is smaller smaller but but too too expensive expensive for for 499 499 price price CS 152 L20 Buses Disks and RAID UC Regents Fall 2005 UCB Users expansion via serial buses Serial Serial Data Data is is sent sent bit bit by by bit bit over over one one logical logical wire wire Serial Serial pros pros and and cons cons Sending data over many wires introduces skew USB USB signals travel on each wire at FireWire FireWire a slightly different speed Ethernet Ethernet Skew limits speed and length of a bus Serial buses have fewer skew issues because When only using one Low cost a small wire there is a they onlyofuse onecost logical number wires bandwidth limit Thus wire less Also cheap wires DIMMs uses many wires and connectors can be CS 152 L20 Buses Disks and RAID UC Regents Fall 2005 UCB Many other buses hidden from user Processor Processor bus bus How How the the CPU CPU talks talks to to everything everything else Not else Bus Bus Not standardize standardize controller controller d d 1 Just Just 1 for for low low cost cost High end High end products products have have two two CS 152 L20 Buses Disks and RAID CPU CPU PowerPC PowerPC G4 G4 Freescale Freescale UC Regents Fall 2005 UCB Uses many standard parallel buses AGP AGP 4X 4X bus bus Graphics Graphics chip chip ATA 100 ATA 100 bus bus For For hard hard disk disk PCI ATA PCI ATA DVD CD DVD CD AGP devices AGP devices ROM ROM can can be be bus bus master master for for Direct Direct Memory Memory Access Access CS 152 L20 Buses Disks and RAID PCI PCI bus bus Boot Boot ROM ROM USB USB 2 2 UC Regents Fall 2005 UCB CS 152 L20 Buses Disks and RAID UC Regents Fall 2005 UCB CS 152 L20 Buses Disks and RAID UC Regents Fall 2005 UCB Source Source iSuppli iSuppli corporation corporation Parts Parts cost cost in in volume volume 274 69 274 69 Parts Parts manufacturing manufacturing cost cost 283 37 283 37 Reminder No Checkoff this Friday Final checkoff the following TAs will provide Friday secret MIPS machine code tests Bonus points if these tests run by end of section If not TAs give you test code to use over weekend Final report due following Monday CS 152 L20 Buses Disks and RAID UC Regents Fall 2005 UCB Disks CS 152 L20 Buses Disks and RAID UC Regents Fall 2005 UCB Trick use bar magnets to code bits Symb Symb ol ol N S N S CS 152 L20 Buses Disks and RAID UC Regents Fall 2005 UCB Write and read bar direction on a disk Longitudinal Longitudinal Recording Recording Today s Today s technology technology Magnets Magnets tend tend to to erase erase each each other other 0 1 0 0 0 1 Disk Disk surface surface Perpendicul Perpendicul ar ar Recording Recording Coming Coming CS 152 L20 Buses Disks and RAID 0 10 0 01 UC Regents Fall 2005 UCB Read head signal from spinning disk CS 152 L20 Buses Disks and RAID UC Regents Fall 2005 UCB Data block written on a sector of a track Each Each ring ring is is a a track track A track A track is is divided divided into sectors into sectors A sector codes A sector codes a a fixed fixed of of bytes bytes ex ex 4K 4K blocks blocks Outer tracks Outer tracks hold hold
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