Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32UC Regents Fall 2005 © UCBCS 152 L20: Buses, Disks, and RAID2005-11-8John Lazzaro (www.cs.berkeley.edu/~lazzaro)CS 152 Computer Architecture and EngineeringLecture 20 – Buses, Disks, and RAIDwww-inst.eecs.berkeley.edu/~cs152/TAs: David Marquardt and Udam SainiUC Regents Fall 2005 © UCBCS 152 L20: Buses, Disks, and RAIDLast Time: Multithreading, Multiple Cores(2) Threads on two cores share memory via L2 cache operations.Much faster than2 CPUs on 2 chips.(2) Threads on two cores share memory via L2 cache operations.Much faster than2 CPUs on 2 chips.(1) Threads on two cores that use shared libraries conserve L2 memory.(1) Threads on two cores that use shared libraries conserve L2 memory.UC Regents Fall 2005 © UCBCS 152 L20: Buses, Disks, and RAIDToday: Buses, Disks, and RAIDBuses: Shared physical wires that act to communicate signals between several devices (often ”peripherals”)Disks: Store bits as the orientation of miniature “bar magnets” on a rotating platter. A mechanical device: slow and prone to failure.Buses let computers be expandable: add more memory, a better graphics card, a webcam, etc.Buses let computers be expandable: add more memory, a better graphics card, a webcam, etc.UC Regents Fall 2005 © UCBCS 152 L20: Buses, Disks, and RAIDProperties of bus structures ...Control lines: Controls transactions, signals what is on data linesData lines: Carries information across the interfaceBuses are an abstraction for communication: helps designers compose large, complex systems.UC Regents Fall 2005 © UCBCS 152 L20: Buses, Disks, and RAIDBuses are defined in layers ...Transaction ProtocolsSignal Timing on WiresWiresElectrical PropertiesMechanical PropertiesExample: DIMM DRAM bus. The name of every wire is defined in a standards document.JEDEC: Joint Electron Device Engineering Council. Makes the DRAM bus standards.UC Regents Fall 2005 © UCBCS 152 L20: Buses, Disks, and RAIDLower levels of DRAM bus specificationTransaction ProtocolsSignal Timing on WiresWiresElectrical PropertiesMechanical PropertiesIdeally, DIMMs made by any manufacturer should fit into any compliant socket, and work.UC Regents Fall 2005 © UCBCS 152 L20: Buses, Disks, and RAIDUpper levels of DRAM bus specificationTransaction ProtocolsSignal Timing on WiresWiresElectrical PropertiesMechanical PropertiesCollaboration between DRAM manufacturers(Samsung, Micron) and DRAM users (Intel, Cisco, ... ).UC Regents Fall 2005 © UCBCS 152 L20: Buses, Disks, and RAIDBus wires shared between many DIMMSApple Xserve G5 - has 8 DIMM slots, to support 8GB.Memory controller is the only “bus master” - it can start transactions on the bus, but the DIMMs cannot.DIMMs respond to transaction requests. Since memory controller is only bus master, and there are a small number of DIMM slots, bus sharing is easy: use dedicated wires to each slot.UC Regents Fall 2005 © UCBCS 152 L20: Buses, Disks, and RAIDBuses: pros and cons ...+++ Low cost. One set of wires from memory controller can support up to 8 DIMMs.--- Latency of bus increases with length of wires (needed to reach all 8 DIMM sockets), and the loading of 8 DIMMs. Must design for worst-case (8 DIMMs), even if only 1 DIMM is present.--- Shared wires limit maximum bandwidth from memory. If memory controller had 8 sets of dedicated wires, one per DIMM, memory bandwidth would be much better (but more expensive).UC Regents Fall 2005 © UCBCS 152 L20: Buses, Disks, and RAIDBuses turn a CPU into a productCase Study: Mac MiniUC Regents Fall 2005 © UCBCS 152 L20: Buses, Disks, and RAIDConstraints: Size, low price (499 USD)Size fixed by the “form factor” (physical size) of desktop DIMMS. Laptop DRAM is smaller, but too expensive for $499 price.Size fixed by the “form factor” (physical size) of desktop DIMMS. Laptop DRAM is smaller, but too expensive for $499 price.UC Regents Fall 2005 © UCBCS 152 L20: Buses, Disks, and RAIDUsers expansion via serial busesSerial: Data is sent “bit by bit” over one logical wire.Serial: Data is sent “bit by bit” over one logical wire.+++ Low cost: a small number of wires cost less. Also, cheap wires and connectors can be used, since skew is less a problem.--- When only using one wire, there is a bandwidth limit. Thus, DIMMs uses many wires(a ”parallel” bus, not “serial”).USB, FireWire Ethernet.USB, FireWire Ethernet.+++ Sending data over many wires introduces “skew” - signals travel on each wire at a slightly different speed. Skew limits speed and length of a bus. Serial buses have fewer skew issues, because they only use one logical wire.Serial pros and cons:Serial pros and cons:UC Regents Fall 2005 © UCBCS 152 L20: Buses, Disks, and RAIDProcessor bus.How the CPUtalks to everything else. Not standardized.Processor bus.How the CPUtalks to everything else. Not standardized.CPU: PowerPC G4 (Freescale)CPU: PowerPC G4 (Freescale)Bus controller. Just 1 for low cost. High-end products have two: fast North Bridge, slow South Bridge.Bus controller. Just 1 for low cost. High-end products have two: fast North Bridge, slow South Bridge.Many other buses hidden from userUC Regents Fall 2005 © UCBCS 152 L20: Buses, Disks, and RAIDUses many standard parallel buses ...AGP 4X bus.Graphics chip.AGP 4X bus.Graphics chip.PCI bus: Boot ROM, USB 2.PCI bus: Boot ROM, USB 2.ATA/100 bus.For hard disk,DVD/CD ROM.ATA/100 bus.For hard disk,DVD/CD ROM.PCI, ATA, AGP devices can be bus master, for Direct Memory Access (DMA). Disk can write RAM directly.PCI, ATA, AGP devices can be bus master, for Direct Memory Access (DMA). Disk can write RAM directly.UC Regents Fall 2005 © UCBCS 152 L20: Buses, Disks, and RAIDUC Regents Fall 2005 © UCBCS 152 L20: Buses, Disks, and RAIDParts + manufacturing cost: $283.37Parts + manufacturing cost: $283.37Parts cost in volume: $274.69Parts cost in volume: $274.69Source: iSuppli corporationSource: iSuppli corporationUC Regents Fall 2005 © UCBCS 152 L20: Buses, Disks, and RAIDReminder: No Checkoff this Friday!TAs will provide “secret” MIPS machine code tests.Bonus points ifthese tests run byend of section. If not, TAs give you test code to use over weekendFinal checkoff the following Friday ... Final report due following Monday, 11:59 PMUC
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