CS152 Computer Architecture and Engineering Lecture 7 Design Notebook Single Cycle Control 2004 09 21 John Lazzaro www cs berkeley edu lazzaro Dave Patterson www cs berkeley edu patterson www inst eecs berkeley edu cs152 CS 152 L07 Single Cycle 2 1 UC Regents Fall 2004 UCB Review 5 steps to design a processor 1 Analyze instruction set datapath requirements 2 Select set of datapath components establish clock methodology 3 Assemble datapath meeting the requirements 4 Analyze implementation of each instruction to determine setting of control points that effects the register transfer 5 Assemble the control logic This Lecture MIPS makes it easier Instructions same size Source registers immediates always in same place Operations always on registers immediates Single cycle datapath CPI 1 CCT long CS 152 L07 Single Cycle 2 2 UC Regents Fall 2004 UCB Why should you keep a design notebook Keep track of the design decisions and the reasons behind them Otherwise it will be hard to debug and or refine the design Write it down so that can remember in long project 2 weeks 2 yrs Others can review notebook to see what happened Record insights you have on certain aspect of the design as they come up Record of the different design debug experiments Memory can fail when very tired Industry practice learn from others mistakes CS 152 L07 Single Cycle 2 3 UC Regents Fall 2004 UCB Why do we keep it on line You need to force yourself to take notes Open a window and leave an editor running while you work 1 Acts as reminder to take notes 2 Makes it easy to take notes 1 2 will actually do it Take advantage of the window system s cut and paste features It is much easier to read your typing than your writing Also paper log books have problems Limited capacity end up with many books May not have right book with you at time vs networked screens Can use computer to search files index files to find what looking for CS 152 L07 Single Cycle 2 4 UC Regents Fall 2004 UCB How should you do it Keep it simple DON T make it so elaborate that you won t use fonts layout Separate the entries by dates type date command in another window and cut paste Start day with problems going to work on today Record output of simulation into log with cut paste add date May help sort out which version of simulation did what Record key email with cut paste Record of what works doesn t helps team decide what went wrong after you left Index write a one line summary of what you did at end of each day CS 152 L07 Single Cycle 2 5 UC Regents Fall 2004 UCB On line Notebook Example Refer to the handout Example of On Line Log Book on CS 152 home page http www inst eecs berkeley edu cs152 handouts online notebook example html CS 152 L07 Single Cycle 2 6 UC Regents Fall 2004 UCB Recap Putting it All Together 1 Cycle Datapath RegDst PCSrc busA Rw Ra Rb 32 32 bit Registers busB 32 imm16 16 32 32 0 1 32 Data In Clk 0 32 WrEn Adr Data Memory Mux 00 5 ExtOp CS 152 L07 Single Cycle 2 7 MemtoReg Rt Mux imm16 5 Rs Extender Adder PC Ext Clk ALUctr MemWr Zero ALU Mux PC Adder 32 Clk Imm16 0 RegWr 5 busW Rd Rd Rt 1 4 Rt Instruction 31 0 0 15 Rs 11 15 Adr 16 20 21 25 Inst Memory 1 ALUSrc UC Regents Fall 2004 UCB Recap The MIPS lite Subset ADD and subtract 31 op 6 bits add rd rs rt sub rd rs rt OR Imm ori rt rs imm16 26 31 26 op 6 bits 21 rs 5 bits 21 rs 5 bits 16 rt 5 bits 11 rd 5 bits 6 shamt 5 bits 16 rt 5 bits 0 funct 6 bits 0 immediate 16 bits LOAD and STORE lw rt rs imm16 sw rt rs imm16 BRANCH beq rs rt imm16 CS 152 L07 Single Cycle 2 8 UC Regents Fall 2004 UCB Meaning of the Control MemWr zero sign ExtOp Signals 1 write memory ALUsrc 0 regB 1 immed MemtoReg 0 ALU 1 Mem ALUctr add sub or RegDst 0 rt 1 rd RegWr 1 write register RegDst RegWr 5 5 Rs 5 Rt 0 1 32 Data In 32 ExtOp ALUSrc Clk 32 0 Mux CS 152 L07 Single Cycle 2 9 16 Extender imm16 32 ALU busA Rw Ra Rb 32 32 bit Registers busB 32 Mux 32 Clk MemWr MemtoReg 0 1 busW ALUctr Zero Rd Rt WrEn Adr 1 Data Memory UC Regents Fall 2004 UCB Two equivalent ways to specify control AddU Control Control Control line 0 line 1 line n A B SubU Control line 0 Control line 1 ORI Control line n LW SW BEQ X Y AddU SubU ORI A LW SW BEQ B X Y Rotate about 45degree axis Book does left version Fig 5 18 p 308 Book combines all ALU instructions as R format vs separate instructions add Good news lecture different view than book We ll do right by committee 1 at a time CS 152 L07 Single Cycle 2 10 UC Regents Fall 2004 UCB Setting PC Source Control Signal0 PC PC 4 PCSrc 1 PC PC 4 SignExt Im16 2 b00 Later in lecture higher level connection between mux and branch cond Answer AddU SubU ORI PCSrc Adr 4 00 Adder imm16 PC Mux Adder PC Ext Clk CS 152 L07 Single Cycle 2 11 Inst Memory 0 1 2 3 4 5 6 7 8 9 0 0 0 0 0 0 1 1 X LW SW BEQ 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 X X X X None of the above 0 1 1 1 1 1 1 X 1 UC Regents Fall 2004 UCB Meaning of the Control 0 zero 1 sign MemWr ExtOp Signals 1 write memory ALUsrc 0 regB 1 immed MemtoReg 0 ALU 1 Mem ALUctr add sub or RegDst 0 rt 1 rd RegWr 1 write register RegDst RegWr 5 5 Rt 16 CS 152 L07 Single Cycle 2 13 Extender imm16 32 0 1 32 Data In 32 ExtOp ALUSrc Clk 32 0 Mux busA Rw Ra Rb 32 32 bit Registers busB 32 Mux Clk 5 Rs ALU 32 MemWr MemtoReg 0 1 busW ALUctr Zero Rd Rt WrEn Adr 1 Data Memory UC Regents Fall 2004 UCB Specify ALU source mux Control ALUsrc 0 reg as ALU B input 1 immediate as ALU B input Rd Rt 5 32 5 Rs 5 Rt imm16 16 Extender Clk 32 0 Mux busA Rw Ra Rb 32 32 bit Registers busB 32 ALU busW Answer 0 1 1 32 Data In 32 ExtOp CS 152 L07 Single Cycle 2 14 0 1 2 3 4 5 6 7 8 9 AddU SubU ORI 0 …
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