CS152 Computer Architecture and Engineering Lecture 18 Memory and CachesRecap: Who Cares About the Memory Hierarchy?Recap: Static RAM CellRecap: 1-Transistor Memory Cell (DRAM)Recap: Memory Hierarchy of a Modern Computer SystemRecap: Memory SystemsThe Big Picture: Where are We Now?Classical DRAM Organization (square)DRAM logical organization (4 Mbit)DRAM physical organization (4 Mbit)Logic Diagram of a Typical DRAMDRAM Read TimingDRAM Write TimingMain Memory PerformanceSlide 15Increasing Bandwidth - InterleavingSlide 17Independent Memory BanksFewer DRAMs/System over TimeFast Page Mode OperationKey DRAM Timing ParametersDRAMs over TimeDRAM HistoryDRAM v. Desktop Microprocessors CulturesAdministrative IssuesRecall: Levels of the Memory HierarchyCache performance equations:Impact on PerformanceThe Art of Memory System DesignExample: 1 KB Direct Mapped Cache with 32 B BlocksBlock Size TradeoffExtreme Example: single lineAnother Extreme Example: Fully AssociativeSet Associative CacheDisadvantage of Set Associative CacheA Summary on Sources of Cache MissesSource of Cache Misses QuizSources of Cache Misses AnswerFour Questions for Caches and Memory HierarchyQ1: Where can a block be placed in the upper level?Q2: How is a block found if it is in the upper level?Q3: Which block should be replaced on a miss?Q4: What happens on a write?Write Buffer for Write ThroughWrite Buffer SaturationWrite-miss Policy: Write Allocate versus Not AllocateImpact of Memory Hierarchy on AlgorithmsQuicksort vs. Radix as vary number keys: InstructionsQuicksort vs. Radix as vary number keys: Instrs & TimeQuicksort vs. Radix as vary number keys: Cache missesHow Do you Design a Cache?Impact on Cycle TimeWhat happens on a Cache miss?Improving Cache Performance: 3 general options3Cs Absolute Miss Rate (SPEC92)2:1 Cache Rule3Cs Relative Miss Rate1. Reduce Misses via Larger Block Size2. Reduce Misses via Higher AssociativityExample: Avg. Memory Access Time vs. Miss Rate3. Reducing Misses via a “Victim Cache”4. Reducing Misses via “Pseudo-Associativity”5. Reducing Misses by Hardware Prefetching6. Reducing Misses by Software Prefetching Data7. Reducing Misses by Compiler OptimizationsSummary #1 / 3:Summary #2 / 3: The Cache Design SpaceSummary #3 / 3: Cache Miss Optimization4/7/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec18.1CS152Computer Architecture and EngineeringLecture 18Memory and CachesApril 7, 1999John Kubiatowicz (http.cs.berkeley.edu/~kubitron)lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/4/7/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec18.2µProc60%/yr.(2X/1.5yr)DRAM9%/yr.(2X/10 yrs)110100100019801981198319841985198619871988198919901991199219931994199519961997199819992000DRAMCPU1982Processor-MemoryPerformance Gap:(grows 50% / year)PerformanceTime“Moore’s Law”Processor-DRAM Memory Gap (latency)Recap: Who Cares About the Memory Hierarchy?4/7/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec18.3Recap: Static RAM Cell6-Transistor SRAM Cellbit bitword(row select)bit bitword°Write:1. Drive bit lines (bit=1, bit=0)2.. Select row°Read:1. Precharge bit and bit to Vdd2.. Select row3. Cell pulls one line low4. Sense amp on column detects difference between bit and bitreplaced with pullupto save area100 14/7/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec18.4Recap: 1-Transistor Memory Cell (DRAM)°Write:•1. Drive bit line•2.. Select row°Read:•1. Precharge bit line to Vdd•2.. Select row•3. Cell and bit line share charges-Very small voltage changes on the bit line•4. Sense (fancy sense amp)-Can detect changes of ~1 million electrons•5. Write: restore the value °Refresh•1. Just do a dummy read to every cell.row selectbit4/7/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec18.5Recap: Memory Hierarchy of a Modern Computer System°By taking advantage of the principle of locality:•Present the user with as much memory as is available in the cheapest technology.•Provide access at the speed offered by the fastest technology.ControlDatapathSecondaryStorage(Disk)ProcessorRegistersMainMemory(DRAM)SecondLevelCache(SRAM)On-ChipCache1s 10,000,000s (10s ms)Speed (ns): 10s 100s100sGsSize (bytes):Ks MsTertiaryStorage(Disk)10,000,000,000s (10s sec)Ts4/7/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec18.6Recap: Memory Systems°Two Different Types of Locality:•Temporal Locality (Locality in Time): If an item is referenced, it will tend to be referenced again soon.•Spatial Locality (Locality in Space): If an item is referenced, items whose addresses are close by tend to be referenced soon.°By taking advantage of the principle of locality:•Present the user with as much memory as is available in the cheapest technology.•Provide access at the speed offered by the fastest technology.°DRAM is slow but cheap and dense:•Good choice for presenting the user with a BIG memory system°SRAM is fast but expensive and not very dense:•Good choice for providing the user FAST access time.4/7/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec18.7°The Five Classic Components of a Computer°Today’s Topics: •Recap last lecture•Continue discussion of DRAM•Cache Review•Advanced Cache•Virtual Memory•Protection•TLBThe Big Picture: Where are We Now? ControlDatapathMemoryProcessorInputOutput4/7/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec18.8Classical DRAM Organization (square)rowdecoderrowaddressColumn Selector & I/O CircuitsColumnAddressdataRAM Cell Arrayword (row) selectbit (data) lines°Row and Column Address together: •Select 1 bit a timeEach intersection representsa 1-T DRAM Cell4/7/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec18.9DRAM logical organization (4 Mbit)°Square root of bits per RAS/CASColumn DecoderSense Amps & I/OMemory Array(2,048 x 2,048)A0…A10…11DQWord LineStorage Cell4/7/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec18.10Block Row Dec.9 : 512RowBlockRow Dec.9 : 512Column Address…BlockRow Dec.9 : 512BlockRow Dec.9 : 512…Block 0 Block 3…I/OI/OI/OI/OI/OI/OI/OI/ODQAddress28 I/Os8 I/OsDRAM physical organization (4 Mbit)4/7/99 ©UCB Spring 1999CS152 / Kubiatowicz Lec18.11ADOE_L256K x 8DRAM9 8WE_L°Control Signals (RAS_L, CAS_L, WE_L, OE_L) are all active low°Din and Dout are combined (D):•WE_L is asserted (Low), OE_L is disasserted (High)-D serves as the data input pin•WE_L is disasserted (High), OE_L is asserted (Low)-D is the data output pin°Row and column addresses share the same pins (A)•RAS_L goes low: Pins A are latched in as
View Full Document
Unlocking...