Review CS152 Computer Architecture and Engineering Lecture 6 Single Cycle Design Notebook Timing key concept critical path 2004 09 16 John Lazzaro www cs berkeley edu lazzaro Dave Patterson Xilinx Physical yet configurable www cs berkeley edu patterson www inst eecs berkeley edu cs152 CS 152 L06 Single Cycle 1 1 UC Regents Fall 2004 UCB Outline Single clock cycle per instruction Data path resource used at most once per instruction Need to replicate some data path resources if need more than once memory ALU adders Timing Testing of Single Cycle CS 152 L06 Single Cycle 1 2 UC Regents Fall 2004 UCB How to Design a Processor step by step 1 Analyze instruction set datapath requirements the meaning of each instruction is given by the register transfers datapath must include storage element for ISA registers possibly more datapath must support each register transfer 2 Select set of datapath components and establish clocking methodology 3 Assemble datapath meeting the requirements 4 Analyze implementation of each instruction to determine setting of control points that effects the register transfer Single Cycle Datapath 5 generic steps on next slide 5 Assemble the control logic See how far we get this lecture finish next time Design Notebook CS 152 L06 Single Cycle 1 3 UC Regents Fall 2004 UCB The MIPS Instruction Formats R type 31 6 bits rs 26 op I type 31 J type 6 bits 5 bits rs 26 op 6 bits 5 bits rt 21 5 bits 16 0 rd shamt funct 5 bits 5 bits 6 bits 0 imme diate rt 5 bits 16 bits 0 addU rd rs rt subU rd rs rt ori rt rs imm16 31 31 UC Regents Fall 2004 UCB beq rs rt imm16 CS 152 L06 Single Cycle 1 6 21 rs 5 bits 26 op lw rt rs imm16 sw rt rs imm16 BRANCH 26 op 6 bits 31 LOAD and STORE Word target address 26 bits op operation of the instruction rs rt rd the source and destination register specifiers shamt shift amount funct selects the variant of the operation in the op field address immediate address offset or immediate value target address target address of the jump instruction CS 152 L06 Single Cycle 1 5 ADD and SUB OR Immediate The different fields are UC Regents Fall 2004 UCB Step 1a The MIPS lite Subset for today All MIPS instructions are 32 bits long The three instruction formats 31 26 21 16 11 6 op CS 152 L06 Single Cycle 1 4 op 5 bits 21 op 6 bits 5 bits 16 5 bits 0 funct 6 bits 0 16 bits 0 imme diate 5 bits 21 rs 6 shamt 5 bits imme diate rt 5 bits 26 11 rd 5 bits 16 rt rs 6 bits 31 21 rs 6 bits 26 16 rt 5 bits 16 bits 16 rt 5 bits 0 imme diate 16 bits UC Regents Fall 2004 UCB Lectures vs Chapter 5 COD 3 e Difficult complaint for textbook author Lecturing directly from the textbook Good news These lectures differ from book Book Lectures MIPS lite subset MIPS lite subset Add Sub LW SW BEQ OR AND SLT J Addu Subu LW SW BEQ ORi Using Hardware Description Lang All start by fetching the instruction op rs rt rd shamt funct MEM PC op rs rt Imm16 inst MEM PC HDL description ADDU R rd R rs R rt PC PC 4 SUBU R rd R rs R rt PC PC 4 PC PC 4 ORi R rt R rs zero ext Imm16 LOAD R rt MEM R rs sign ext Imm16 PC PC 4 STORE MEM R rs sign ext Imm16 R rt PC PC 4 BEQ CS 152 L06 Single Cycle 1 7 UC Regents Fall 2004 UCB Step 1 Requirements of the Instruction Set Memory if R rs R rt PC PC 4 sign ext Imm16 2 b00 else PC PC 4 CS 152 L06 Single Cycle 1 8 UC Regents Fall 2004 UCB Step 2 Components of the Datapath Combinational Logic Elements One for instructions one for data Storage Elements State Registers 32 x 32bit Clocking methodology Read RS Read RT Write RT or RD PC Sign Extender for immediate field Add and Sub register or Extended Immediate Add 4 or Extended Immediate to PC CS 152 L06 Single Cycle 1 9 UC Regents Fall 2004 UCB Combinational Logic Elements Basic Building Blocks CarryIn Adder A B Adder 32 32 32 Sum Carry Select 32 MUX multi B plexor A B 32 32 Y OP 32 32 CS 152 L06 Single Cycle 1 11 ALU ALU MUX A 32 Result to add values to chose between values to do add subtract or UC Regents Fall 2004 UCB CS 152 L06 Single Cycle 1 10 UC Regents Fall 2004 UCB Storage Element Register Basic Building Block Register Similar to the D Flip Flop except Write Enable Data Out Data In N N N bit input and output Write Enable input Clk Write Enable negated 0 Data Out will not change asserted 1 Data Out will become Data In CS 152 L06 Single Cycle 1 12 UC Regents Fall 2004 UCB Storage Element Register File Storage Element Idealized Memory RWRA RB Write Enable 5 5 5 Register File consists of 32 registers Two 32 bit output busses busA 32 32 32 bit Registers busB Register is selected by 32 RA number selects the register to put on busA data busA and busB One 32 bit input bus busW busW 32 Clk RB number selects the register to put on busB data RW number selects the register to be written via busW data when Write Enable is 1 Memory word is selected by Address Data In 32 Clk DataOut 32 Address selects the word to put on Data Out Write Enable 1 address selects the memory word to be written via the Data In bus The CLK input is a factor ONLY during write operation During read operation behaves as a combinational logic block The CLK input is a factor ONLY during write operation During read operation Register File behaves as a combinational logic block Address valid Data Out valid after access time RA or RB valid busA or busB valid after access time CS 152 L06 Single Cycle 1 13 UC Regents Fall 2004 UCB Administrivia Last mini lab Friday Lab 2 Design Document due Friday Should already have groups Reading Sections 5 1 to 5 4 5 8 Appendix B of COD 3e CS 152 L06 Single Cycle 1 15 UC Regents Fall 2004 UCB Hold CS 152 L06 Single Cycle 1 14 UC Regents Fall 2004 UCB Computers In The News Intel shifts focus to multicore chip performance 9 7 04 S F Chronicle Intel Corp which has led the charge in the gigahertz race is expected to change its tune Excess heat in PC microprocessors has become an increasingly difficult problem to solve as chipmakers crank up the frequency of the tiny transistors to boost performance Dual core will be part of Intel s big theme which shows Intel is changing direction from focusing on faster and faster gigahertz to …
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