CS 152 Computer Architecture and Engineering Lecture 27 Mid Term II Review 2005 5 3 John Lazzaro www cs berkeley edu lazzaro TAs Ted Hong and David Marquardt www inst eecs berkeley edu cs152 CS 152 L26 Synchronization UC Regents Spring 2005 UCB CS 152 What s left Today Mid term Review HKN This time more of an overview style Thursday 5 5 Midterm II 6 PM to 9 PM 320 Soda No class on Thursday No electronic devices no notes Peer Review For final project Please send by Friday at 5 PM Tuesday 5 10 Final presentations Deadline to bring up grading issues Tues 5 10 5PM Contact John at lazzaro eecs CS 152 L26 Synchronization UC Regents Spring 2005 UCB CS 152 Computer Architecture and Engineering Lecture 19 Error Correcting Codes 2005 3 31 John Lazzaro www cs berkeley edu lazzaro TAs Ted Hong and David Marquardt www inst eecs berkeley edu cs152 CS 152 L26 Synchronization UC Regents Spring 2005 UCB Understand how Hamming Codes work We write Later we read D D D P D P P 0 1 1 0 01 1 D D D P D P P 0 1 0 0 01 1 Cosmic ray hit D1 But how do we know that On readout we compute P xor D xor D xor D 1 P xor D xor D xor D 1 P xor D xor D xor D 0 Note we number the least significant bit with 1 not 0 0 is reserved for no errors CS 152 L26 Synchronization 0 xor 0 xor 0 xor 0 xor 1 xor 1 xor 7 654 3 2 1 D D D P D P P 0 1 0 0 01 1 0 1 xor 0 0 xor 0 1 xor P P P b101 5 What does 5 mean The position of the flipped bit To repair just flip it back UC Regents Spring 2005 UCB Understand Parity Code math Simple case Two 1KB blocks of data A and B Create a third block C Parity codes C A xor B do xor on each bit of block Read all three blocks If A or B is not available but C is regenerate A or B A C xor B B C xor A The math is easy the trick is system design Examples RAID voice over IP parity FEC CS 152 L26 Synchronization UC Regents Spring 2005 UCB Understand Parity Code system design The disk will tell you this block does not exist or the disk is dead by returning an error code when you do a read If we know this will happen in advance what can we do at the OS or application level CS 152 L26 Synchronization Often applications number packets as they send them by adding a sequence number to packet header Receivers detect a break in the number sequence UC Regents Spring 2005 UCB Understand checksum big picture Can checksums detect every possible error Answer No for a 16 bit checksum there are many possible packets that have the same checksum If you are unlucky enough to have your transmission errors convert a block into another block with the same checksum value you will not detect the error CS 152 L26 Synchronization UC Regents Spring 2005 UCB CS 152 Computer Architecture and Engineering Lecture 20 Advanced Processors I 2005 4 5 John Lazzaro www cs berkeley edu lazzaro TAs Ted Hong and David Marquardt www inst eecs berkeley edu cs152 CS 152 L26 Synchronization UC Regents Spring 2005 UCB Understand superpipeline performance NAL OF SOLID STATE CIRCUITS VOL 36 NO 11 NOVEMBER 2001 Seconds Program Instructions Program Cycles Instruction Seconds Cycle Q Could adding pipeline stages reduce CPI for an application A Yes due to these problems ARM XScale 8 stages Fig 2 where the state boundaries are indicated by croprocessor pipeline organization CS 152 L26 Synchronization CPI Problem Possible Solution Taken branches cause longer stalls Branch prediction loop unrolling Cache misses take more clock cycles Larger caches add prefetch opcodes to ISA UC Regents Spring 2005 UCB Understand branch prediction in depth IF Fetch ID Decode EX ALU IR 0x4 IR MEM IR WB IR I Cache Instr Mem PC D Q Addr Data Branch Predictor Predictions A control instr Taken or Not Taken The PC a branch targets CS 152 L26 Synchronization We update the PC based on the outputs of the branch predictor If it is perfect pipe stays full Dynamic Predictors a cache of branch history Time t1 Inst IF I1 I2 I3 I4 I5 I6 t2 t3 t4 t5 ID IF EX ID IF MEM WB t6 t7 t8 EX stage computes if branch is taken If we predicted incorrectly these instructions MUST NOT complete UC Regents Spring 2005 UCB In Depth means down to this level Prediction for next branch 1 take 0 not take D Q Was last prediction correct 1 yes 0 no D Q We do not change the prediction the first time it is incorrect Why ADDI R4 R0 11 loop SUBI R4 R4 1 BNE R4 R0 loop CS 152 L26 Synchronization This branch taken 10 times then not taken once end of loop The next time we enter the loop we would like to predict take the first time through UC Regents Spring 2005 UCB Understand lockstep superscalar concept 012 3 4 550 8A BA 789 9 9 M4 I7 IJ N I 8 OPQR 7PQR KL 7 DD 7N8A 7D Example Superscalar MIPS Fetches 2 instructions at a time If first integer and second floating point issue in same cycle Integer instruction Two issues per cycle CS 152 L26 Synchronization LD LD LD LD LD SD SD SD SD F0 0 R1 F6 8 R1 F10 16 R1 F14 24 R1 F18 32 R1 0 R1 F4 8 R1 F8 16 R1 F12 24 R1 F16 FP instruction ADDD F4 F0 F2 ADDD F8 F6 F2 ADDD F12 F10 F2 ADDD F16 F14 F2 ADDD F20 F18 F2 One issue per cycle UC Regents Spring 2005 UCB CS 152 Computer Architecture and Engineering Lecture 21 Advanced Processors II Ou t of o C PU rde r d will esig n 2005 4 7 NOT app e ar o e n xa m John Lazzaro s u ffi H W w www cs berkeley edu lazzaro as c ie n t TAs Ted Hong and David Marquardt www inst eecs berkeley edu cs152 CS 152 L26 Synchronization UC Regents Spring 2005 UCB 0 123 4 5 66 1 UnderstandQ 9 I BF Precise Interrupts Definition or exception 0 0 0 1 2 3 3 0 4 0 0 01102 31 44 562 3 67 3 246 8 3 44 239740 0 3 01102 31 562 3 1 05 0 74 20 0 05567 405 0 05 35 0 75385 9 35 50 5 Follows from the contract between the architect and the programmer CS 152 L26 Synchronization UC Regents Spring 2005 UCB in the context of Static Pipelines 8 A BC D 120 3 4 5 67 8 0 9 P9 G 1 0 L98 0 6C R 0 J 6C0A 440 D 1 …
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