UC Regents Spring 2005 © UCBCS 152 L26: Synchronization2005-5-3John Lazzaro (www.cs.berkeley.edu/~lazzaro)CS 152 Computer Architecture and EngineeringLecture 27 – Mid-Term II Reviewwww-inst.eecs.berkeley.edu/~cs152/TAs: Ted Hong and David MarquardtUC Regents Spring 2005 © UCBCS 152 L26: SynchronizationCS 152: What’s left ...Today: Mid-term Review, HKN ...Thursday 5/5: Midterm II, 6 PM to 9 PM, 320 Soda.Tuesday 5/10: Final presentations.This time, more of an overview style ...No class on Thursday. Deadline to bring up grading issues:Tues 5/10@ 5PM. Contact John at lazzaro@eecsPeer Review: For final project.Please send by Friday at 5 PM.No electronic devices, no notes ...UC Regents Spring 2005 © UCBCS 152 L26: Synchronization2005-3-31John Lazzaro (www.cs.berkeley.edu/~lazzaro)CS 152 Computer Architecture and EngineeringLecture 19 – Error Correcting Codeswww-inst.eecs.berkeley.edu/~cs152/TAs: Ted Hong and David MarquardtUC Regents Spring 2005 © UCBCS 152 L26: SynchronizationUnderstand how Hamming Codes workCosmic ray hit D1. But how do we know that?D₃D₂D₁P₂D₀P₁P₀On readout we compute:P₀ xor D₃ xor D₁ xor D₀ = 1 xor 0 xor 0 xor 0 = 1 P₁ xor D₃ xor D₂ xor D₀ = 1 xor 0 xor 1 xor 0 = 0P₂ xor D₃ xor D₂ xor D₁ = 0 xor 0 xor 1 xor 0 = 10 11 0 0 1 1We write:D₃D₂D₁P₂D₀P₁P₀0 01 0 0 1 1Later, we read:P₂P₁P₀ = b101 = 5What does “5” mean?0 01 0 0 1 1The position of the flipped bit!To repair, just flip it back ...D₃D₂D₁P₂D₀P₁P₀1436 57 2Note: we number the least significant bit with 1, not 0! 0 is reserved for “no errors”.UC Regents Spring 2005 © UCBCS 152 L26: SynchronizationUnderstand Parity Code math ...Simple case: Two 1KB blocks of data (A and B)Create a third block, C:C = A xor B (do xor on each bit of block)Read all three blocks. If A or B is not available but C is, regenerate A or B:A = C xor B B = C xor A The math is easy: the trick is system design! Examples: RAID, voice-over-IP parity FEC.“Parity codes”UC Regents Spring 2005 © UCBCS 152 L26: SynchronizationUnderstand Parity Code system designThe disk will tell you “this block does not exist” or “the disk is dead”, by returningan error code when you do a read.Often, applications number packets as they send them, by adding a “sequence number” to packet header. Receivers detect a “break” in the number sequence ...If we know this will happen in advance, what can we do, at the OS or application level?UC Regents Spring 2005 © UCBCS 152 L26: SynchronizationUnderstand checksum “big picture” ...Can checksums detect every possible error?Answer: No -- for a 16-bit checksum, there are many possible packets that have the same checksum. If you are unlucky enough to have your transmission errors convert a block into another block with the same checksum value, you will not detect the error!UC Regents Spring 2005 © UCBCS 152 L26: Synchronization2005-4-5John Lazzaro (www.cs.berkeley.edu/~lazzaro)CS 152 Computer Architecture and EngineeringLecture 20 – Advanced Processors Iwww-inst.eecs.berkeley.edu/~cs152/TAs: Ted Hong and David MarquardtUC Regents Spring 2005 © UCBCS 152 L26: SynchronizationUnderstand superpipeline performance SecondsProgram InstructionsProgram=SecondsCycle InstructionCycles1600 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36, NO. 11, NOVEMBER 2001Fig. 1. Process SEM cross section.The process was raised from [1] to limit standby power.Circuit design and architectural pipelining ensure low voltageperformance and functionality. To further limit standby currentin handheld ASSPs, a longer poly target takes advantage of theversus dependence and source-to-body bias is usedto electrically limit transistor in standby mode. All corenMOS and pMOS transistors utilize separate source and bulkconnections to support this. The process includes cobalt disili-cide gates and diffusions. Low source and drain capacitance, aswell as 3-nm gate-oxide thickness, allow high performance andlow-voltage operation.III. ARCHITECTUREThe microprocessor contains 32-kB instruction and datacaches as well as an eight-entry coalescing writeback buffer.The instruction and data cache fill buffers have two and fourentries, respectively. The data cache supports hit-under-missoperation and lines may be locked to allow SRAM-like oper-ation. Thirty-two-entry fully associative translation lookasidebuffers (TLBs) that support multiple page sizes are providedfor both caches. TLB entries may also be locked. A 128-entrybranch target buffer improves branch performance a pipelinedeeper than earlier high-performance ARM designs [2], [3].A. Pipeline OrganizationTo obtain high performance, the microprocessor core utilizesa simple scalar pipeline and a high-frequency clock. In additionto avoiding the potential power waste of a superscalar approach,functional design and validation complexity is decreased at theexpense of circuit design effort. To avoid circuit design issues,the pipeline partitioning balances the workload and ensures thatno one pipeline stage is tight. The main integer pipeline is sevenstages, memory operations follow an eight-stage pipeline, andwhen operating in thumb mode an extra pipe stage is insertedafter the last fetch stage to convert thumb instructions into ARMinstructions. Since thumb mode instructions [11] are 16 b, twoinstructions are fetched in parallel while executing thumb in-structions. A simplified diagram of the processor pipeline isFig. 2. Microprocessor pipeline organization.shown in Fig. 2, where the state boundaries are indicated bygray. Features that allow the microarchitecture to achieve highspeed are as follows.The shifter and ALU reside in separate stages. The ARM in-struction set allows a shift followed by an ALU operation in asingle instruction. Previous implementations limited frequencyby having the shift and ALU in a single stage. Splitting this op-eration reduces the critical ALU bypass path by approximately1/3. The extra pipeline hazard introduced when an instruction isimmediately followed by one requiring that the result be shiftedis infrequent.Decoupled Instruction Fetch. A two-instruction deep queue isimplemented between the second fetch and instruction decodepipe stages. This allows stalls generated later in the pipe to bedeferred by one or more cycles in the earlier pipe stages, therebyallowing instruction fetches to proceed when the pipe is stalled,and also relieves stall speed paths in the instruction fetch
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