CS152 Computer Architecture and Engineering Lecture 2 Review of MIPS ISA and Performance January 27 2003 John Kubiatowicz http cs berkeley edu kubitron lecture slides http inst eecs berkeley edu cs152 1 27 03 UCB Spring 2003 CS152 Kubiatowicz Lec2 1 Review Organization All computers consist of five components Processor 1 datapath and 2 control 3 Memory I O 4 Input devices and 5 Output devices Datapath and Control typically on on chip Not all memory is created equally Cache fast expensive memory close to processor Main memory less expensive memory Input and output I O devices have the messiest organization Wide range of speed graphics vs keyboard Wide range of requirements speed standard cost Least amount of research so far 1 27 03 UCB Spring 2003 CS152 Kubiatowicz Lec2 2 Review Instruction Set Design Review It s all about communication Pentium III Chipset Proc software Caches Busses adapters instruction set Memory Controllers I O Devices hardware Disks Displays Keyboards Networks All have interfaces organizations Which is easier to change design Um It s the network stupid 1 27 03 UCB Spring 2003 CS152 Kubiatowicz Lec2 3 1 27 03 UCB Spring 2003 CS152 Kubiatowicz Lec2 4 Instruction Set Architecture What Must be Specified Instruction Fetch Instruction Decode Operand Fetch Execute Result Store Instruction Format or Encoding how is it decoded Location of operands and result where other than memory how many explicit operands how are memory operands located which can or cannot be in memory ISA Choices Data type and Size Operations what are supported Successor instruction jumps conditions branches Next fetch decode execute is implicit Instruction 1 27 03 UCB Spring 2003 CS152 Kubiatowicz Lec2 5 Typical Operations little change since 1960 Data Movement Arithmetic Shift 1 27 03 1 27 03 Rank instruction integer binary decimal or FP Add Subtract Multiply Divide shift left right rotate left right not and or set clear Control Jump Branch unconditional conditional Subroutine Linkage call return Interrupt trap return Synchronization test set atomic r m w String Graphics MMX search translate parallel subword ops 4 16bit add UCB Spring 2003 CS152 Kubiatowicz Lec2 6 Top 10 80x86 Instructions Load from memory Store to memory memory to memory move register to register move input from I O device output to I O device push pop to from stack Logical UCB Spring 2003 Integer Average Percent total executed 1 load 22 2 conditional branch 20 3 compare 16 4 store 12 5 add 8 6 and 6 7 sub 5 8 move register register 4 9 call 1 10 return 1 Total 96 Simple instructions dominate instruction frequency CS152 Kubiatowicz Lec2 7 1 27 03 UCB Spring 2003 CS152 Kubiatowicz Lec2 8 Operation Summary Compilers and Instruction Set Architectures Support these simple instructions since they will dominate the number of instructions executed orthogonality no special registers few special cases all operand modes available with any data type or instruction type completeness support for a wide range of operations and target applications regularity no overloading for the meanings of instruction fields streamlined resource needs easily determined load store add subtract move register register and shift compare equal compare not equal branch jump call return 1 27 03 UCB Spring 2003 Ease of compilation Register Assignment is critical too Easier if lots of registers CS152 Kubiatowicz Lec2 9 Basic ISA Classes 1 27 03 UCB Spring 2003 Comparing Number of Instructions Most real machines are hybrids of these Code sequence for C A B for four classes of instruction sets Accumulator 1 register 1 address add A acc acc mem A 1 x address addx A acc acc mem A x add tos tos next 3 address add A B add A B C Register load store Accumulator Push A Load A Load R1 A Load R1 A Push B Add B Add R1 B Load R2 B EA A EA A EA B Add Store C Store C R1 EA A B EA C Pop C General Purpose Register can be memory memory 2 address Register register memory Stack Stack 0 address CS152 Kubiatowicz Lec2 10 Add R3 R1 R2 Store C R3 Load Store 3 address add Ra Rb Rc Ra Rb Rc load Ra Rb Ra mem Rb store Ra Rb mem Rb Ra Comparison Bytes per instruction Number of Instructions Cycles per instruction 1 27 03 UCB Spring 2003 CS152 Kubiatowicz Lec2 11 1 27 03 UCB Spring 2003 CS152 Kubiatowicz Lec2 12 General Purpose Registers Dominate Example MIPS I Registers 1975 2000 all machines use general purpose registers Advantages of registers registers are faster than memory registers are easier for a compiler to use e g A B C D E F can do multiplies in any order vs stack Programmable storage registers can hold variables memory traffic is reduced so program is sped up since registers are faster than memory code density improves since register named with fewer bits than memory location 1 27 03 UCB Spring 2003 CS152 Kubiatowicz Lec2 13 Memory Addressing Processor 2 32 x bytes of memory 31 x 32 bit GPRs R0 0 32 x 32 bit FP regs paired DP HI LO PC 1 27 03 r0 r1 r31 PC lo hi 0 CS152 Kubiatowicz Lec2 14 UCB Spring 2003 Addressing Objects Endianess and Alignment Big Endian address of most significant byte word address xx00 Big End of word IBM 360 370 Motorola 68k MIPS Sparc HP PA Memory Continuous Linear Address Space Little Endian address of least significant byte word address xx00 Little End of word Intel 80x86 DEC Vax DEC Alpha Windows NT little endian byte 0 Since 1980 almost every machine uses addresses to level of 8 bits byte 3 2 questions for design of ISA Since could read a 32 bit word as four loads of bytes from sequential byte addresses or as one load word from a single byte address How do byte addresses map onto words Can a word be placed on any byte boundary 2 1 0 lsb msb 0 0 big endian byte 0 1 2 1 2 3 3 Aligned Alignment require that objects fall on address that is multiple of their size Not Aligned 1 27 03 UCB Spring 2003 CS152 Kubiatowicz Lec2 15 1 27 03 UCB Spring 2003 CS152 Kubiatowicz Lec2 16 Addressing Modes Addressing Mode Usage ignore register mode Addressing mode Example Meaning 3 programs measured on machine with all address modes VAX Register Add R4 R3 R4m R4 R3 Displacement 42 avg 32 to 55 Immediate Add R4 3 R4 m R4 3 Immediate 33 avg 17 to 43 Displacement Add R4 100 R1 R4 m R4 Mem 100 R1 Register indirect Add R4 R1 Indexed Base Add R3 R1 R2 R3 m R3 Mem R1 R2 Direct or absolute Add R1 1001 R1 m R1 Mem 1001 Memory indirect Add R1 R3 R1 m R1 Mem Mem R3 Post increment Add R1 R2 R1 m R1 Mem R2 R2 m R2 d Pre decrement Add R1 R2 R2 m R2 d R1 m R1 Mem R2 Scaled Scaled 7 avg 0
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