1/27/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec2.1January 27, 2003John Kubiatowicz (http.cs.berkeley.edu/~kubitron)lecture slides: http://inst.eecs.berkeley.edu/~cs152/CS152Computer Architecture and EngineeringLecture 2Review of MIPS ISA and Performance1/27/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec2.2Review: Organization All computers consist of five components• Processor: (1) datapath and (2) control• (3) Memory• I/O: (4) Input devices and (5) Output devices Datapath and Control typically on on chip Not all “memory” is created equally• Cache: fast (expensive) memory close to processor• Main memory: less expensive memory Input and output (I/O) devices have the messiest organization:• Wide range of speed: graphics vs. keyboard• Wide range of requirements: speed, standard, cost ... • Least amount of research (so far) 1/27/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec2.3Review: It’s all about communication All have interfaces & organizations Um…. It’s the network stupid???!ProcCachesBussesMemoryI/O Devices:ControllersadaptersDisksDisplaysKeyboardsNetworksPentium III Chipset1/27/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec2.4Review: Instruction Set Designinstruction setsoftwarehardwareWhich is easier to change/design???1/27/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec2.5Instruction Set Architecture: What Must be Specified?InstructionFetchInstructionDecodeOperandFetchExecuteResultStoreNextInstruction Instruction Format or Encoding• how is it decoded? Location of operands and result• where other than memory?• how many explicit operands?• how are memory operands located?• which can or cannot be in memory? Data type and Size Operations• what are supported Successor instruction• jumps, conditions, branches• fetch-decode-execute is implicit!1/27/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec2.6ISAChoices1/27/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec2.7Typical Operations (little change since 1960)Data MovementLoad (from memory)Store (to memory)memory-to-memory moveregister-to-register moveinput (from I/O device)output (to I/O device)push, pop (to/from stack)Arithmeticinteger (binary + decimal) or FPAdd, Subtract, Multiply, DivideLogicalnot, and, or, set, clearShiftshift left/right, rotate left/rightControl (Jump/Branch)unconditional, conditionalSubroutine Linkagecall, returnInterrupttrap, returnSynchronizationtest & set (atomic r-m-w)Stringsearch, translateGraphics (MMX)parallel subword ops (4 16bit add)1/27/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec2.8Top 10 80x86 InstructionsRankinstructionInteger Average Percent total executed1 load 22%2 conditional branch 20%3 compare 16%4 store 12%5 add 8%6 and 6%7 sub 5%8 move register-register 4%9 call 1%10 return 1%Total 96%Simple instructions dominate instruction frequency1/27/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec2.9Operation SummarySupport these simple instructions, since they will dominate the number of instructions executed: load, store, add, subtract, move register-register, and, shift, compare equal, compare not equal, branch, jump, call, return;1/27/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec2.10Compilers and Instruction Set Architectures• Ease of compilation• orthogonality: no special registers, few special cases, all operand modes available with any data type or instruction type• completeness: support for a wide range of operations and target applications• regularity: no overloading for the meanings of instruction fields• streamlined: resource needs easily determined• Register Assignment is critical too• Easier if lots of registers1/27/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec2.11Basic ISA ClassesAccumulator (1 register):1 addressadd A acc ← acc + mem[A]1+x address addx A acc ← acc + mem[A + x]Stack:0 address add tos ← tos + nextGeneral Purpose Register (can be memory/memory):2 address add A B EA[A] ← EA[A] + EA[B]3 address add A B C EA[A] ←ΕΑ[B] + EA[C]Load/Store:3 address add Ra Rb Rc Ra ← Rb + Rcload Ra Rb Ra ← mem[Rb]store Ra Rb mem[Rb] ← RaComparison:Bytes per instruction? Number of Instructions? Cycles per instruction?Most real machines are hybrids of these:1/27/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec2.12Comparing Number of InstructionsCode sequence for (C = A + B) for four classes of instruction sets:StackAccumulatorRegister (load-store)Push A Load A Load R1,APush B Add B Load R2,BAdd Store CRegister (register-memory)Load R1,AAdd R1,BStore C, R1 Add R3,R1,R2Pop C Store C,R31/27/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec2.13General Purpose Registers Dominate° 1975-2000 all machines use general purpose registers° Advantages of registers• registers are faster than memory• registers are easier for a compiler to use-e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order vs. stack• registers can hold variables- memory traffic is reduced, so program is sped up (since registers are faster than memory)-code density improves (since register named with fewer bits than memory location)1/27/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec2.14Example: MIPS I Registers Programmable storage• 2^32 x bytes of memory• 31 x 32-bit GPRs (R0 = 0)• 32 x 32-bit FP regs (paired DP)• HI, LO, PC0r0r1°°°r31PClohi1/27/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec2.15Memory AddressingSince 1980 almost every machine uses addresses to level of 8-bits (byte) 2 questions for design of ISA:• Since could read a 32-bit word as four loads of bytes from sequential byte addresses or as one load word from a single byteaddress, How do byte addresses map onto words?• Can a word be placed on any byte boundary?ProcessorMemory:Continuous LinearAddress Space?1/27/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec2.16Addressing Objects: Endianess and Alignment Big Endian: address of most significant byte = word address (xx00 = Big End of word)• IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA Little Endian:address of least significant byte = word address(xx00 = Little End of word)• Intel 80x86, DEC Vax, DEC Alpha (Windows NT)msblsb3 2 1 0little endian byte 00 1 2 3big endian byte 0Alignment: require that objects fall on address that is multiple of their size.0 1 2 3AlignedNotAligned1/27/03 ©UCB Spring 2003CS152 / Kubiatowicz Lec2.17Addressing
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