CS 152 Computer Architecture and Engineering Lecture 4 Testing and Teamwork 2006 9 7 Con o n g rats La b 1 John Lazzaro www cs berkeley edu lazzaro TAs Udam Saini and Jue Sun www inst eecs berkeley edu cs152 CS 152 L4 Testing and Teamwork UC Regents Fall 2006 UCB Last Time Single Cycle Processors Instr Mem Combinational Logic Only Gates No Flip Flops Equal 32 Addr Just specify logic functions Data RegDest PCSrc RegWr ExtOp MemToReg ALUsrc 5 5 5 RegFile rs1 rd1 rs2 32 ws 32 wd RegDest 32 rd2 ALUctr op 32 Data Memory 32 WE CS 152 L4 Testing and Teamwork ExtOp A L U 32 Addr Equal 32 Dout Din Ext RegWr MemWr 32 WE MemToReg ALUsrc MemWr UC Regents Fall 2006 UCB Today Testing Processors Teamwork Making a processor test plan Unit testing techniques State machine testing Teamwork Lessons learned from previous CS 152 classes CS 152 L4 Testing and Teamwork UC Regents Fall 2006 UCB Lecture Focus Functional Design Test IEEE JOURNAL OF SOLID STATE CIRCUITS VOL 36 NO 11 NOVEMBER 2001 testing goal g n i r ct u fa u n a The processor m t No design s t s te correctly executes programs written in the supported subset of the MIPS ISA I P C d e s e e p r s u k t c c C l o m i n g le Up c o Intel XScale ARM Pipeline IEEE Journal of Solid State Circuits 36 11 November 2001 Fig 2 Microprocessor pipeline organization CS 152 L4 Testing and Teamwork UC Regents Fall 2006 UCB Four Types of Testing CS 152 L4 Testing and Teamwork UC Regents Fall 2006 UCB Big Bang Complete Processor Testing 1600 IEEE JOURNAL OF SOLID STATE CIRCUITS VOL 36 NO 11 NOVEMBE Top down testing how it works complete processor testing Lab 1 Assemble the complete processor Fig 1 Execute test program suite on the processor Process SEM cross section The process was raised from 1 to limit standby power Circuit design and architectural pipelining ensure low voltage performance and functionality To further limit standby current in handheld ASSPs a longer poly target takes advantage of the versus dependence and source to body bias is used to electrically limit transistor in standby mode All core nMOS and pMOS transistors utilize separate source and bulk connections to support this The process includes cobalt disilicide gates and diffusions Low source and drain capacitance as well as 3 nm gate oxide thickness allow high performance and low voltage operation Check results Bottom up testing This is how TAs test on checkoff days CS 152 L4 Testing and Teamwork III ARCHITECTURE Fig 2 Microprocessor pipeline organization shown in Fig 2 where the UC state boundaries are indicate Regents Fall 2006 UCB Methodical Approach Unit Testing 1600 IEEE JOURNAL OF SOLID STATE CIRCUITS VOL 36 NO 11 NOVEMBE Top down testing how it works complete processor testing Remove a block from the design Fig 1 unit testing Bottom up testing Test it in isolation against specification Process SEM cross section The process was raised from 1 to limit standby power Circuit design and architectural pipelining ensure low voltage performance and functionality To further limit standby current in handheld ASSPs a longer poly target takes advantage of the versus dependence and source to body bias is used to electrically limit transistor in standby mode All core nMOS and pMOS transistors utilize separate source and bulk connections to support this The process includes cobalt disilicide gates and diffusions Low source and drain capacitance as well as 3 nm gate oxide thickness allow high performance and low voltage operation What if the specification has a bug What if team members do not use the exact same specification III A CS 152 L4 Testing and Teamwork RCHITECTURE Fig 2 Microprocessor pipeline organization shown in Fig 2 where the UC state boundaries are indicate Regents Fall 2006 UCB Climbing the Hierarchy Multi unit Testing 1600 IEEE JOURNAL OF SOLID STATE CIRCUITS VOL 36 NO 11 NOVEMBE Top down testing how it works complete processor testing multi unit testing unit testing Bottom up testing Remove connected blocks from design Fig 1 Test in isolation against specification Process SEM cross section The process was raised from 1 to limit standby power Circuit design and architectural pipelining ensure low voltage performance and functionality To further limit standby current in handheld ASSPs a longer poly target takes advantage of the versus dependence and source to body bias is used to electrically limit transistor in standby mode All core nMOS and pMOS transistors utilize separate source and bulk connections to support this The process includes cobalt disilicide gates and diffusions Low source and drain capacitance as well as 3 nm gate oxide thickness allow high performance and low voltage operation How to choose partition How to create specification CS 152 L4 Testing and Teamwork III ARCHITECTURE Fig 2 Microprocessor pipeline organization shown in Fig 2 where the UC state boundaries are indicate Regents Fall 2006 UCB Processor Testing with Self Checking Units 1600 IEEE JOURNAL OF SOLID STATE CIRCUITS VOL 36 NO 11 NOVEMBE Top down testing how it works complete processor testing Add self checking to units processor testing with self checks multi unit testing unit testing Bottom up testing Fig 1 Perform complete processor testing Process SEM cross section The process was raised from 1 to limit standby power Circuit design and architectural pipelining ensure low voltage performance and functionality To further limit standby current in handheld ASSPs a longer poly target takes advantage of the versus dependence and source to body bias is used to electrically limit transistor in standby mode All core nMOS and pMOS transistors utilize separate source and bulk connections to support this The process includes cobalt disilicide gates and diffusions Low source and drain capacitance as well as 3 nm gate oxide thickness allow high performance and low voltage operation Good for Xilinx ModelSim Why not use self checks for all tests III A CS 152 L4 Testing and Teamwork RCHITECTURE Fig 2 Microprocessor pipeline organization shown in Fig 2 where the UC state boundaries are indicate Regents Fall 2006 UCB Testing Verification vs Diagnostics Top down testing complete processor testing processor testing with self checks multi unit testing unit testing Bottom up testing CS 152 L4 Testing and Teamwork Verification A yes no answer to the question Does the processor have one more bug Diagnostics Clues to help find and fix the bug Which testing types are good for verification For diagnostics UC Regents
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