Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38Slide 39Slide 40Slide 41Slide 42Slide 43Slide 44Slide 45Slide 46Slide 47Slide 48Slide 49Slide 50Slide 51UC Regents Fall 2005 © UCBCS 152 L26: Mid-Term II Review2005-12-1John Lazzaro (www.cs.berkeley.edu/~lazzaro)CS 152 Computer Architecture and EngineeringLecture 26 – Mid-Term II Reviewwww-inst.eecs.berkeley.edu/~cs152/TAs: David Marquardt and Udam SainiUC Regents Fall 2005 © UCBCS 152 L26: Mid-Term II ReviewCS 152: What’s left ...Tuesday 12/6: Mid-term II, 6:00-9:00 PM, 310 Soda. No class 11-12:30 that day.No electronic devices, no notes,leave backpacks in front of class ...Today: HKN, Mid-term II Review.Homework II due in class.Thursday 12/8: Final presentations.Email slides to cs152-staff@cory by 11:50 PM.UC Regents Fall 2005 © UCBCS 152 L26: Mid-Term II ReviewMid-Term II Facts ...1 202 123 124 165 206 107 10Tot100#PointsSeven problems: One fewer than Mid-term I.Show you know how it works Like Mid-term I, but ...Less writing than Mid-term IBut perhaps more thinking ...We will choose 7 problems ...From the 8 “candidates” in this lecture ... bug insurance.UC Regents Fall 2005 © UCBCS 152 L26: Mid-Term II ReviewCache ProblemUC Regents Fall 2005 © UCBCS 152 L26: Mid-Term II ReviewRecall: Set Associative CacheCache Tag (26 bits)Index(2 bits)Byte Select (4 bits)Cache block halved to keep # cached bits constant.ValidCache BlockCache BlockCache Tags Cache DataCache BlockCache BlockCache TagsValidCache DataEx: 0x01=HitRight=HitLeftReturn bytes of “hit” set member“N-way” set associative -- N is number of blocks for each color16 bytes16 bytesPowerPC 970: 32K 2-wayset associative L1 D-cacheUC Regents Fall 2005 © UCBCS 152 L26: Mid-Term II Review Recall: Cache Block Replacement After a cache read miss, if there are no empty cache blocks, which block should be removed from the cache?A randomly chosen block?Easy to implement, how well does it work?The Least Recently Used (LRU) block? Appealing,but hard to implement.Size Random LRU16 KB5.7% 5.2%64 KB2.0% 1.9%256 KB1.17% 1.15%Miss Rate for 2-way Set Associative CacheAlso,tryotherLRUapprox.Part of your state machine decides which block to replace.UC Regents Fall 2005 © UCBCS 152 L26: Mid-Term II Review Recall: Write Policy, Write Allocate ...Write-Through Write-BackPolicyData written to cache blockalso written to lower-level memoryWrite data only to the cacheUpdate lower level when a block falls out of the cacheDo read misses produce writes?No YesDo repeated writes make it to lower level?Yes NoRelated issue: do writes to blocks not in the cache get put in the cache (”write-allocate”) or not?State machine design (1) Write-back puts most write logic in cache-miss machine. (2) Write-through isolates writing in its own state machine.UC Regents Fall 2005 © UCBCS 152 L26: Mid-Term II ReviewCache problem ...We specify memory system architecture: Ex: 4-way set associative, write through, allocate on write, random replacement ...We specify cache and memory contentsIncluding tags, valid bits, etc ...We specify a machine language programProgram will be short ...You show final cache and memory stateThe program is designed to test your knowledge about how caching works.UC Regents Fall 2005 © UCBCS 152 L26: Mid-Term II ReviewTLB ProblemUC Regents Fall 2005 © UCBCS 152 L26: Mid-Term II ReviewRecall: Address translation - how it works“Physical Addresses”CPU MemoryA0-A31 A0-A31D0-D31 D0-D31DataTLB also contains ASID andkernel/supervisor bits for virtual addressVirtual Physical“Virtual Addresses”TranslationLook-AsideBuffer(TLB)Translation Look-Aside Buffer (TLB)A small fully-associative cache of mappings from virtual to physical addressesFast common case: Virtual address is in TLB, process has permission to read/write it.UC Regents Fall 2005 © UCBCS 152 L26: Mid-Term II ReviewV=0 pages either reside on disk or have not yet been allocated.OS handles V=0“Page fault”In this example,physical and virtual pages must be the same size!Recall: The TLB caches page table entriesTLBPage Table2013virtual addresspage off2frame page250physical addresspage offTLB caches page table entries.MIPS handles TLB misses in software (random replacement). Other machines use hardware.for ASIDPhysicalframeaddressUC Regents Fall 2005 © UCBCS 152 L26: Mid-Term II ReviewRecall MIPS R4000 TLB details ...“Physical Addresses”CPUMemorySystemA0-A31 A0-A31D0-D31 D0-D31DataTranslationLook-AsideBuffer(TLB)Virtual Physical“Virtual Addresses”Physical space larger than virtual space!Checked againstCPO ASIDUC Regents Fall 2005 © UCBCS 152 L26: Mid-Term II ReviewTLB problem ...We specify a TLB architecture: Ex: 16-entry TLB, random replacement,4KB and 8KB page sizes, 8-bit ASID, etc.We specify initial TLB contentsVirtual fields, physical fields, etc ...We specify machine language programsPrograms will be short ...You describe TLB behavior during executionThe program is designed to test your knowledge about how TLBs work.P&H 3/e: 7.4, 7.5, 7. 7UC Regents Fall 2005 © UCBCS 152 L26: Mid-Term II ReviewECC ProblemUC Regents Fall 2005 © UCBCS 152 L16: Error Correcting CodesRecall error correction: Hamming CodesRichard Hamming.Computing pioneer.Famous quote:“Computers are not for numbers. Computers are for understanding.”UC Regents Fall 2005 © UCBCS 152 L16: Error Correcting CodesRecall: Basic structure of the codeCosmic ray hit D1. But how do we know that?D₃D₂D₁P₂D₀P₁P₀On readout we compute:P₀ xor D₃ xor D₁ xor D₀ = 1 xor 0 xor 0 xor 0 = 1 P₁ xor D₃ xor D₂ xor D₀ = 1 xor 0 xor 1 xor 0 = 0P₂ xor D₃ xor D₂ xor D₁ = 0 xor 0 xor 1 xor 0 = 10 11 0 0 1 1We write:D₃D₂D₁P₂D₀P₁P₀0 01 0 0 1 1Later, we read:P₂P₁P₀ = b101 = 5What does “5” mean?0 01 0 0 1 1The position of the flipped bit!To repair, just flip it back ...D₃D₂D₁P₂D₀P₁P₀1436 57 2Note: we number the least significant bit with 1, not 0! 0 is reserved for “no errors”.UC Regents Fall 2005 © UCBCS 152 L16: Error Correcting CodesRecall: Choosing # of parity bits ...0 Consider 4 bit words.P₂P₁P₀Observation: The parity bits need to encode the “no error” condition, plus a number for each bit (both data and parity
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