CS 152 Computer Architecture and Engineering Lecture 26 Mid Term II Review 2005 12 1 John Lazzaro www cs berkeley edu lazzaro TAs David Marquardt and Udam Saini www inst eecs berkeley edu cs152 CS 152 L26 Mid Term II Review UC Regents Fall 2005 UCB CS 152 What s left Today HKN Mid term II Review Homework II due in class Tuesday 12 6 Mid term II 6 00 9 00 PM 310 Soda No class 11 12 30 that day No electronic devices no notes leave backpacks in front of class 12 8 Final presentations Thursday Email slides to cs152 staff cory by 11 50 PM CS 152 L26 Mid Term II Review UC Regents Fall 2005 UCB Mid Term II Facts Seven problems One fewer than Mid term I Show you know how it works Like Mid term I but Less writing than Mid term I But perhaps more thinking We will choose 7 problems From the 8 candidates in this lecture bug insurance CS 152 L26 Mid Term II Review Points 1 20 2 12 3 12 4 16 5 20 6 10 7 10 Tot 100 UC Regents Fall 2005 UCB Cache Problem CS 152 L26 Mid Term II Review UC Regents Fall 2005 UCB Recall Set Associative Cache N way set associative N is number of blocks for each color Byte Select Index Cache Tag 26 bits 4 bits 2 bits Ex 0x01 Cache Data ValidCache Tags Cache TagsValid Cache Data Cache Block Cache Block Cache Block 16 bytes Hit Left Hit Right Cache Block 16 bytes Return bytes of hit set member Cache block halved to keep cached bits CS 152 L26 Mid Term II Review PowerPC 970 32K 2way UC Regents Fall 2005 UCB Recall Cache Block Replacement After a cache read miss if there are no empty cache blocks which block should be removed from the cache The Least Recently A randomly chosen Used LRU block block Appealing Easy to implement but hard to for 2 way Set Associative Cachehow Miss Rate implement well does it work Also Size Random LRU try 16 KB 5 7 5 2 other 64 KB 2 0 1 9 LRU appro 256 KB 1 17 1 15 x Part of your state machine decides which block CS 152 L26 Mid Term II Review to replace UC Regents Fall 2005 UCB Recall Write Policy Write Allocate Write Through Write Back Policy Data written to cache block also written to lower level memory Write data only to the cache Update lower level when a block falls out of the cache Do read misses produce writes No Yes Do repeated writes make it to lower level Yes No Related issue do writes to blocks not in the cache get put in the cache writeallocate or not State machine design 1 Write back puts most write logic in cache miss machine 2 Write through isolates writing in its CS 152 L26 Mid Term II Review UC Regents Fall 2005 UCB Cache problem We specify memory system architecture Ex 4 way set associative write through allocate on write random replacement We specify cache and memory contents Including tags valid bits etc We specify a machine language program Program will be short You show final cache and memory state The program is designed to test your knowledge about how caching works CS 152 L26 Mid Term II Review UC Regents Fall 2005 UCB TLB Problem CS 152 L26 Mid Term II Review UC Regents Fall 2005 UCB Recall Address translation how it works Physical Addresses Virtual Addresses A0 A31 Virtual CPU D0 D31 Data Physical Translation Look Aside Buffer TLB A0 A31 Memory D0 D31 Translation Look Aside Buffer TLB A small fully associative cache of mappings from virtual to physical addresses TLB also contains ASID and kernel supervisor bits for virtual address Fast common case Virtual address is in TLB process has permission to read write it CS 152 L26 Mid Term II Review UC Regents Fall 2005 UCB Recall The TLB caches page table entries In this example physical and virtual pages must be the same size TLB caches page table entries virtual address page Physic al frame addres s for ASID off Page Table 2 0 1 3 TLB frame page 2 2 0 5 CS 152 L26 Mid Term II Review physical address page off MIPS handles TLB misses in software random replacement Other V 0 pages either reside on disk or have not yet been allocated OS handles UC Regents Fall 2005 UCB V 0 Recall MIPS R4000 TLB details Physical Addresses Virtual Addresses A0 A31 Virtual CPU D0 D31 Data Checke d against CPO ASID CS 152 L26 Mid Term II Review Physical Translation Look Aside Buffer TLB A0 A31 Memory System D0 D31 Physical space larger than virtual space UC Regents Fall 2005 UCB TLB problem P H 3 e 7 4 7 5 7 7 We specify a TLB architecture Ex 16 entry TLB random replacement 4KB and 8KB page sizes 8 bit ASID etc We specify initial TLB contents Virtual fields physical fields etc We specify machine language programs Programs will be short You describe TLB behavior during execution The program is designed to test your knowledge about how TLBs work CS 152 L26 Mid Term II Review UC Regents Fall 2005 UCB ECC Problem CS 152 L26 Mid Term II Review UC Regents Fall 2005 UCB Recall error correction Hamming Codes Richard Hamming Computing pioneer Famous quote Computers are not for numbers Computers are CS 152 L16 Error Correcting Codes UC Regents Fall 2005 UCB Recall Basic structure of the code D D D P D P P 0 1 1 0 01 1 We Cosmic ray write hit D1 But D D D P D P P Later we how do we 0 1 0 0 01 1 read know that On readout we compute P xor D xor D xor D 1 P1 xor D xor D xor D 1 0P xor D xor D xor D 0 1 Note we number the least significant bit with 1 not 0 0 is reserved for no errors CS 152 L16 Error Correcting Codes 0 xor 0 xor 0 xor 0 xor 1 xor 1 xor 7 654 3 2 1 D D D P D P P 0 1 0 0 01 1 0 xor 0 xor 0 xor P P P b101 5 What does 5 mean The position of the flipped bit To repair just UC Regents Fall 2005 UCB Recall Choosing of parity bits Consider 4 bit words D D D D 0 1 10 Add 3 parity bits P P P Observation The parity bits need to encode the no error condition plus a number for each bit both data and parity bits For p parity bits and d data bits d p 1 2 CS 152 L16 Error Correcting Codes p UC Regents Fall 2005 UCB Recall Why arrange bits as we did Consider 4 bit words D D D D Add 3 parity bits P P P Why do we arrange bits With this order an odd parity means an error in 1 3 …
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