Recap CS 152 Computer Architecture and Engineering Lecture 10 Partition datapath into equal size chunks to minimize cycle time 10 levels of logic between latches Follow same 5 step method for designing real processor Multicycle Controller Design Continued Control is specified by finite state digram Mar 1 1999 John Kubiatowicz http cs berkeley edu kubitron lecture slides http www inst eecs berkeley edu cs152 3 1 99 UCB Spring 1999 CS152 Kubiatowicz Lec10 1 3 1 99 Overview of Control UCB Spring 1999 CS152 Kubiatowicz Lec10 2 Recap Controller Design Control may be designed using one of several initial representations The choice of sequence control and how logic is represented can then be determined independently the control can then be implemented with one of several methods using a structured logic technique The state digrams that arise define the controller for an instruction set processor are highly structured Initial Representation Control reduces to programming this very simple device Finite State Diagram Microprogram Use this structure to construct a simple microsequencer microprogramming Sequencing Control Explicit Next State Microprogram counter Function Dispatch ROMs Logic Representation Logic Equations Implementation Technique hardwired control 3 1 99 PLA UCB Spring 1999 sequencer control Truth Tables microinstruction micro PC ROM sequencer microprogrammed control CS152 Kubiatowicz Lec10 3 datapath control 3 1 99 UCB Spring 1999 CS152 Kubiatowicz Lec10 4 The Big Picture Where are We Now Recap Microprogram Control Specification PC Taken 0000 0001 0001 0010 BEQ 0011 R 0100 0101 ORi 0110 0111 1000 LW 1001 1010 SW 1011 1100 0 1 x x x x x x x x x x x Next IR PC Ops Exec en sel A B Ex Sr ALU S inc 1 load inc zero 1 1 zero 1 0 inc 0 1 fun 1 zero 1 0 inc 0 0 or 1 zero 1 0 inc 1 0 add 1 inc zero 1 0 inc 1 0 add 1 zero 1 0 Mem Write Back R W M M R Wr Dst The Five Classic Components of a Computer Processor Input Control Memory 0 1 1 Datapath Output 0 1 0 1 0 1 1 1 0 Today s Topics Microprogramed control Administrivia Microprogram it yourself 0 1 Exceptions 3 1 99 CS152 Kubiatowicz Lec10 5 UCB Spring 1999 3 1 99 CS152 Kubiatowicz Lec10 6 UCB Spring 1999 Princeton Organization How Effectively are we utilizing our hardware IR Mem PC A Bus B Bus A R rs B R rt S A B S A or ZX S A SX S A SX M Mem S Mem S B next PC P C IR ZX SX Reg File A S Mem B W Bus Single memory for instruction and data access memory utilization 1 3 4 8 R rd S PC PC 4 R rt S PC PC 4 R rd M PC PC 4 PC PC 4 PC PC 4 PC PC SX Sometimes muxes replaced with tri state buses Difference often depends on whether buses are internal to chip muxes or external tri state Example memory is used twice at different times Ave mem access per inst 1 Flw Fsw 1 3 if CPI is 4 8 imem utilization 1 4 8 dmem 0 3 4 8 In this case our state diagram does not change several additional control signals must ensure each bus is only driven by one source on each cycle We could reduce HW without hurting performance 3 1 99 extra control UCB Spring 1999 CS152 Kubiatowicz Lec10 7 3 1 99 UCB Spring 1999 CS152 Kubiatowicz Lec10 8 Our Controller FSM Spec Alternative datapath book Multiple Cycle Datapath Miminizes Hardware 1 memory 1 adder IR MEM PC instruction fetch PC PC 4 RegDst ALUSelA RegWr 1 32 32 5 Rt 0 5 Rd Ra Reg File 32 busW busB 32 1 Mux 0 Extend ExtOp 32 1 Rw 1 Imm 16 3 1 99 busA Rb 2 4 0 32 1 32 2 3 ALU Control R type S A op ZX 0100 0110 S A SX S A SX S A B 1011 0010 1000 Equal Equal MEM S B 1001 1100 R rt S ALUOp UCB Spring 1999 BEQ SW M MEM S 0101 ALUSelB CS152 Kubiatowicz Lec10 9 LW ORi S A fun B R rd S 32 MemtoReg ALU Out WrAdr 32 Din Dout Rt Mux Ideal Memory 1 32 decode A R rs B R rt Zero ALU RAdr Target 0001 0 0 Rs Mux Mux 0 Instruction Reg 32 32 3 1 99 Microprogramming 0111 PC PC SX 00 0011 R rt M 1010 UCB Spring 1999 Write back PC 32 IRWr Execute MemWr 32 0000 BrWr Mux IorD 32 PCSrc PCWrCond Zero Memory PCWr CS152 Kubiatowicz Lec10 10 Sequencer based control unit Control is the hard part of processor design Control Logic Datapath is fairly regular and well organized Memory is highly regular Control is irregular and global Multicycle Datapath Outputs Microprogramming A Particular Strategy for Implementing the Control Unit of a processor by programming at the level of register transfer operations Inputs 1 Types of branching Set state to 0 Dispatch state 1 Use incremented state number Microarchitecture Logical structure and functional capabilities of the hardware as seen by the microprogrammer Adder Address Select Logic Historical Note IBM 360 Series first to distinguish between architecture organization Same instruction set across wide range of implementations each with different cost performance 3 1 99 State Reg UCB Spring 1999 CS152 Kubiatowicz Lec10 11 Opcode 3 1 99 UCB Spring 1999 CS152 Kubiatowicz Lec10 12 Macroinstruction Interpretation Main Memory Variations on Microprogramming User program plus Data ADD SUB AND control field for each control point in the machine this can change DATA seq addr A mux B mux one of these is mapped into one of these AND microsequence control memory compact microinstruction format for each class of microoperation local decode to generate all control points branch seq op add execute ALU op A B R memory mem op S D e g Fetch Calc Operand Addr Fetch Operand s Calculate Save Answer s 3 1 99 CS152 Kubiatowicz Lec10 13 UCB Spring 1999 Horizontal Vertical 3 1 99 CS152 Kubiatowicz Lec10 14 UCB Spring 1999 More Vertical Format Extreme Horizontal 3 1 N3 N2 N1 N0 1 bit for each loadable register enbMAR enbAC src input select dst D E C Incr PC ALU control inputs MUX Multiformat Microcode 6 1 3 0 cond Example mem to reg and ALU to reg should never happen simultaneously encode in single bit which is decoded rather than two separate bits 1 1 NOTE the encoding should be only wide enough so that parallel actions that the datapath supports should still be specifiable in a single microinstruction CS152 Kubiatowicz Lec10 15 next states D E C Makes sense to encode fields to save ROM space UCB Spring 1999 other control fields Some of these may have nothing to do with registers Depending on bus organization many potential control combinations simply wrong i e implies transfers that can never happen at the same time 3 1 99 bus enables register enables Vertical Microcode execution unit CPU Horizontal Microcode 3 dst …
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