3/1/99 ©UCB Spring 1999CS152 / KubiatowiczLec10.1CS 152 Computer Architecture and EngineeringLecture 10Multicycle Controller Design (Continued) Mar 1, 1999John Kubiatowicz (http.cs.berkeley.edu/~kubitron)lecture slides: http://www-inst.eecs.berkeley.edu/~cs152/3/1/99 ©UCB Spring 1999CS152 / KubiatowiczLec10.2Recap° Partition datapath into equal size chunks to minimizecycle time• ~10 levels of logic between latches° Follow same 5-step method for designing “real”processor° Control is specified by finite state digram3/1/99 ©UCB Spring 1999CS152 / KubiatowiczLec10.3Overview of Control° Control may be designed using one of several initialrepresentations. The choice of sequence control, and how logic isrepresented, can then be determined independently; the controlcan then be implemented with one of several methods using astructured logic technique.Initial Representation Finite State Diagram MicroprogramSequencing Control Explicit Next State Microprogram counter Function + Dispatch ROMsLogic Representation Logic Equations Truth TablesImplementation PLA ROMTechnique“hardwired control” “microprogrammed control”3/1/99 ©UCB Spring 1999CS152 / KubiatowiczLec10.4Recap: Controller Design° The state digrams that arise define the controller foran instruction set processor are highly structured° Use this structure to construct a simple“microsequencer”° Control reduces to programming this very simpledevice• microprogrammingsequencercontroldatapath controlmicro-PCsequencermicroinstruction (µ)3/1/99 ©UCB Spring 1999CS152 / KubiatowiczLec10.5Recap: Microprogram Control Specification0000 ? inc 10001 0 load0001 1 inc0010 x zero 1 10011 x zero 1 00100 x inc 0 1 fun 10101 x zero 1 0 0 1 10110 x inc 0 0 or 10111 x zero 1 0 0 1 01000 x inc 1 0 add 11001 x inc 1 0 11010 x zero 1 0 1 1 01011 x inc 1 0 add 11100 x zero 1 0 0 1µPC Taken Next IR PC Ops Exec Mem Write-Backen sel A B Ex Sr ALU S R W M M-R Wr DstR:ORi:LW:SW:BEQ3/1/99 ©UCB Spring 1999CS152 / KubiatowiczLec10.6The Big Picture: Where are We Now? ° The Five Classic Components of a Computer° Today’s Topics:• Microprogramed control• Administrivia• Microprogram it yourself• ExceptionsControlDatapathMemoryProcessorInputOutput3/1/99 ©UCB Spring 1999CS152 / KubiatowiczLec10.7How Effectively are we utilizing our hardware?° Example: memory is used twice, at different times• Ave mem access per inst = 1 + Flw + Fsw ~ 1.3• if CPI is 4.8, imem utilization = 1/4.8, dmem =0.3/4.8° We could reduce HW without hurting performance• extra controlIR <- Mem[PC]A <- R[rs]; B<– R[rt]S <– A + BR[rd] <– S;PC <– PC+4;S <– A + SXM <– Mem[S]R[rd] <– M;PC <– PC+4;S <– A or ZXR[rt] <– S;PC <– PC+4;S <– A + SXMem[S] <- BPC <– PC+4;PC < PC+4; PC < PC+SX;3/1/99 ©UCB Spring 1999CS152 / KubiatowiczLec10.8“Princeton” Organization° Single memory for instruction and data access• memory utilization -> 1.3/4.8° Sometimes, muxes replaced with tri-state buses• Difference often depends on whether buses are internal to chip(muxes) or external (tri-state)° In this case our state diagram does not change• several additional control signals• must ensure each bus is only driven by one source on each cycleRegFileABA-BusB BusIRSW-BusPCnextPCZX SXMem3/1/99 ©UCB Spring 1999CS152 / KubiatowiczLec10.9Alternative datapath (book): Multiple Cycle Datapath° Miminizes Hardware: 1 memory, 1 adderIdealMemoryWrAdrDinRAdr323232DoutMemWr32ALU3232ALUOpALUControlInstruction Reg32IRWr32Reg FileRaRwbusWRb5532busA32busBRegWrRsRtMux01RtRdPCWrALUSelAMux01RegDstMux0132PCMemtoRegExtendExtOpMux01320123416Imm32<< 2ALUSelBMux10Target32ZeroZeroPCWrCondPCSrc BrWr32IorDALU Out3/1/99 ©UCB Spring 1999CS152 / KubiatowiczLec10.10Our Controller FSM SpecIR <= MEM[PC]PC <= PC + 4R-typeA <= R[rs]B <= R[rt]S <= A fun BR[rd] <= SS <= A op ZXR[rt] <= SORiS <= A + SXR[rt] <= MM <= MEM[S]LWS <= A + SXMEM[S] <= BSW“instruction fetch”“decode”ExecuteMemoryWrite-back00000001010001010110011110001001101010111100~EqualEqualBEQPC <= PC + SX || 0000100011S <= A - B3/1/99 ©UCB Spring 1999CS152 / KubiatowiczLec10.11Microprogramming° Control is the hard part of processor design° Datapath is fairly regular and well-organized° Memory is highly regular° Control is irregular and globalMicroprogramming:-- A Particular Strategy for Implementing the Control Unit of a processor by "programming" at the level of register transfer operationsMicroarchitecture:-- Logical structure and functional capabilities of the hardware as seen by the microprogrammerHistorical Note:IBM 360 Series first to distinguish between architecture & organizationSame instruction set across wide range of implementations, each with different cost/performance3/1/99 ©UCB Spring 1999CS152 / KubiatowiczLec10.12Sequencer-based control unitOpcodeState RegInputsOutputsControl LogicMulticycleDatapath1Address Select LogicAdderTypes of “branching”• Set state to 0• Dispatch (state 1)• Use incremented state number3/1/99 ©UCB Spring 1999CS152 / KubiatowiczLec10.13“Macroinstruction” InterpretationMainMemoryexecutionunitcontrolmemoryCPUADDSUBANDDATA...User program plus Datathis can change!AND microsequencee.g., Fetch Calc Operand Addr Fetch Operand(s) Calculate Save Answer(s)one of these ismapped into oneof these3/1/99 ©UCB Spring 1999CS152 / KubiatowiczLec10.14Variations on Microprogramming° “Horizontal” Microcode– control field for each control point in the machine° “Vertical” Microcode– compact microinstruction format for each class ofmicrooperation – local decode to generate all control pointsbranch: µseq-op µaddexecute: ALU-op A,B,Rmemory: mem-op S, Dµseq µaddr A-mux B-mux bus enables register enables HorizontalVertical3/1/99 ©UCB Spring 1999CS152 / KubiatowiczLec10.15Extreme HorizontalinputselectN3 N2N1 N0. . .13Incr PCALU control1 bit for each loadable register enbMAR enbAC . . .Depending on bus organization, many potential control combinations simply wrong, i.e., implies transfers that can never happen at the same time.Makes sense to encode fields to save ROM spaceExample: mem_to_reg and ALU_to_reg should never happen simultaneously; => encode in single bit which is decoded rather than two separate bitsNOTE: the encoding should be only wide enough so that parallel actions that
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