The Big Picture Where are We Now CS152 Computer Architecture and Engineering Lecture 12 The Five Classic Components of a Computer Processor Input Control Memory Introduction to Pipelining Datapath and Control Datapath March 8th 2004 Output Today s Topics John Kubiatowicz www cs berkeley edu kubitron Recap last lecture finish datapath Pipelined Control Do it yourself Pipelined Control Administrivia lecture slides http inst eecs berkeley edu cs152 Hazards Forwarding Exceptions Review MIPS R3000 pipeline 3 8 04 Can pipelining get us into trouble Yes Pipeline Hazards Recap Data Hazards structural hazards attempt to use the same resource two different ways at the same time E g combined washer dryer would be a structural hazard or folder busy doing something else watching TV data hazards attempt to use item before it is ready E g one sock of pair in dryer and one in washer can t fold until get sock from washer through dryer instruction depends on result of prior instruction still in the pipeline control hazards attempt to make a decision before condition is evaulated E g washing football uniforms and need to get proper detergent level need to see after dryer before next load in branch instructions I Fet ch 3 8 04 UCB Spring 2004 DCD MemOpFetch OpFetch IFetch I Fet ch DCD OpFetch IFetch IF DCD EX IF IF 3 8 04 Jump DCD Mem WB DCD EX Store Control Hazard RAW read after write Data Hazard Mem WB DCD EX Mem WB IF DCD IF CS152 Kubiatowicz Lec12 3 DCD Exec Structural Hazard Can always resolve hazards by waiting pipeline control must detect the hazard take action or delay action to resolve hazards CS152 Kubiatowicz Lec12 2 UCB Spring 2004 DCD OF UCB Spring 2004 WAW Data Hazard write after write OF Ex RS Ex Mem WAR Data Hazard write after read CS152 Kubiatowicz Lec12 4 Recall Single cycle control The Main Control generates the control signals during Reg Dec Control Ideal Instruction Memory Control Signals Instruction Rd Rs 5 5 Instruction Address Rt 5 Reg Dec A 32 Rw Ra Rb 32 32 Clk 32 PC Datapath ExtOp ExtOp ALUSrc ALUSrc ALUOp Main Control RegDst MemW r Branch MemtoReg RegWr 3 8 04 CS152 Kubiatowicz Lec12 5 UCB Spring 2004 3 8 04 A MemtoReg RegWr UCB Spring 2004 MemW rBranch MemtoReg RegWr MemtoReg RegWr CS152 Kubiatowicz Lec12 6 WB Ctrl 10 lw r1 r2 35 14 addI r2 r2 3 20 sub r3 r4 r5 24 beq r6 r7 100 30 ori r8 r9 17 34 add r10 r11 r12 100 and r13 r14 15 these addresses are octal PC Next PC D UCB Spring 2004 M S B 3 8 04 Mem Ctrl Reg File im v rw wb Data Mem rs rt v rw wb me MemW r Branch Wr Let s Try it Out Mem Access v rw wb me ex Exec rt rs op Decode IR fun Reg File Inst Mem Datapath Data Stationary Control ALUOp RegDst Mem Mem Wr Register Data In Data Out ID Ex Register Clk Ideal Data Memory IF ID Register B Data Address Exec Ex Mem Register 32 32 bit Registers Clk Control signals for Exec ExtOp ALUSrc are used 1 cycle later Control signals for Mem MemWr Branch are used 2 cycles later Control signals for Wr MemtoReg MemWr are used 3 cycles later Conditions ALU Next Address Data Stationary Control CS152 Kubiatowicz Lec12 7 3 8 04 UCB Spring 2004 CS152 Kubiatowicz Lec12 8 Fetch 14 Decode 10 sub r3 r4 r5 24 beq r6 r7 100 30 ori r8 r9 17 34 add r10 r11 r12 CS152 Kubiatowicz r13 r14 15 Lec12 9 3 8 04 UCB Spring 2004 Reg File r1 r2 35 20 sub r3 r4 r5 24 beq r6 r7 100 30 ori r8 r9 17 34 add r10 r11 r12 CS152 Kubiatowicz r13 r14 15 Lec12 10 100 and addI r2 r2 3 r1 r2 35 sub r3 r4 r5 24 beq r6 r7 100 30 ori r8 r9 17 34 add r10 r11 r12 CS152 Kubiatowicz r13 r14 15 Lec12 11 100 and 3 8 04 Reg File lw r1 24 IF 20 D Data Mem lw ID 14 Mem Access EX 10 M M 10 lw EX 14 addI r2 r2 3 ID 20 sub 24 beq r6 r7 100 30 ori r8 r9 17 34 add r10 r11 r12 IF PC Data Mem B WB Ctrl Mem Ctrl r2 35 Exec r2 4 n addI r2 r2 3 5 3 Decode Inst Mem Reg File IR Next PC 20 PC Next PC D Mem Access B 3 8 04 WB Ctrl M S addI r2 r2 3 UCB Spring 2004 n Mem Ctrl Exec 35 lw r1 Decode Reg File Inst Mem addI r2 r2 3 r2 lw IF 14 Fetch 24 Decode 20 Exec 14 Mem 10 n rt ID 10 14 20 Data Mem D Mem Access r1 r2 35 M S addI r2 r2 3 Fetch 20 Decode 14 Exec 10 2 A Exec Reg File lw WB Ctrl PC 14 Next PC 10 IF 10 n im 100 and UCB Spring 2004 IR rt B PC 3 8 04 n Mem Ctrl Reg File D 2 sub r3 r4 r5 B Next PC M S IR Data Mem A Mem Access im Exec rs rt n Decode WB Ctrl Mem Ctrl Reg File IR Inst Mem n Decode n Reg File n Inst Mem n lw r1 r2 35 Start Fetch 10 UCB Spring 2004 r1 r2 35 r3 r4 r5 CS152 Kubiatowicz r13 r14 15 Lec12 12 100 and D r3 r4 r5 beq r6 r7 100 IF 30 ori r8 r9 17 add r10 r11 r12 CS152 Kubiatowicz r13 r14 15 Lec12 13 3 8 04 10 WB 14 M 20 EX 24 ID 30 34 Mem Ctrl 34 r3 r4 r5 beq r6 r7 100 ori r8 r9 17 add r10 r11 r12 Fill it in yourself CS152 Kubiatowicz ID 100 and r13 r14 15 Lec12 15 3 8 04 sub r3 r4 r5 beq r6 r7 100 ori r8 r9 17 add r10 r11 r12 WB Ctrl Reg File sub D Data Mem r1 r2 35 10 lw 14 addI r2 r2 3 20 sub r3 r4 r5 WB 24 M 30 beq r6 r7 100 ori r8 r9 17 add r10 r11 r12 34 PC addI r2 r2 3 Next PC Data Mem lw 14 Mem Access Exec EX 30 UCB Spring 2004 10 r1 r2 35 addI r2 r2 3 Reg File Reg File IR WB 20 M 24 PC Next PC D Mem Access Exec Reg File Fill it in yourself WB Ctrl Decode Decode Fetch 110 Dcd 104 Ex 100 Mem 30 WB 24 Mem Ctrl lw CS152 Kubiatowicz IF 100 and r13 r14 15 Lec12 14 UCB Spring 2004 Fetch 104 Dcd 100 Ex 30 Mem 24 WB 20 r1 M r2 35 Reg File addI r2 WB Ctrl Inst Mem 100 and 100 sub PC EX 20 ID 24 Data Mem r1 r2 35 addI r2 r2 3 Mem Access lw Next PC 30 WB 10 M 14 r2 3 …
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