CS152Computer Architecture and EngineeringLecture 12Introduction to Pipelining:Datapath and ControlMarch 8th, 2004John Kubiatowicz (www.cs.berkeley.edu/~kubitron)lecture slides: http://inst.eecs.berkeley.edu/~cs152/3/8/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec12.2° The Five Classic Components of a Computer° Today’s Topics: • Recap last lecture/finish datapath• Pipelined Control/ Do it yourself Pipelined Control• Administrivia• Hazards/Forwarding• Exceptions• Review MIPS R3000 pipelineThe Big Picture: Where are We Now? ControlDatapathMemoryProcessorInputOutput3/8/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec12.3Can pipelining get us into trouble?° Yes: Pipeline Hazards• structural hazards: attempt to use the same resource two different ways at the same time- E.g., combined washer/dryer would be a structural hazard or folder busy doing something else (watching TV)• data hazards: attempt to use item before it is ready- E.g., one sock of pair in dryer and one in washer; can’t fold until get sock from washer through dryer- instruction depends on result of prior instruction still in the pipeline• control hazards: attempt to make a decision before condition isevaulated- E.g., washing football uniforms and need to get proper detergent level; need to see after dryer before next load in- branch instructions° Can always resolve hazards by waiting• pipeline control must detect the hazard• take action (or delay action) to resolve hazards3/8/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec12.4Recap: Data HazardsI-Fet ch DCD MemOpFetch OpFetch Exec StoreIFetch DCD ° ° °StructuralHazardI-Fet ch DCD OpFetch JumpIFetch DCD ° ° °Control HazardIF DCD EX Mem WBIF DCD OF Ex MemRAW (read after write) Data HazardWAW Data Hazard(write after write) IF DCD OF Ex RS WAR Data Hazard(write after read) IF DCD EX Mem WBIF DCD EX Mem WB3/8/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec12.5Recall: Single cycle control!DataOutClk5Rw Ra Rb32 32-bitRegistersRdALUClkData InDataAddressIdealDataMemoryInstructionInstructionAddressIdealInstructionMemoryClkPC5Rs5Rt32323232ABNext AddressControlDatapathControl SignalsConditions3/8/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec12.6Data Stationary Control° The Main Control generates the control signals duringReg/Dec• Control signals for Exec (ExtOp, ALUSrc, ...) are used 1 cycle later• Control signals for Mem (MemWr Branch) are used 2 cycles later• Control signals for Wr (MemtoReg MemWr) are used 3 cycles laterIF/ID RegisterID/Ex RegisterEx/Mem RegisterMem/Wr RegisterReg/Dec Exec MemExtOpALUOpRegDstALUSrcBranchMemWrMemtoRegRegWrMainControlExtOpALUOpRegDstALUSrcMemtoRegRegWrMemtoRegRegWrMemtoRegRegWrBranchMemWrBranchMemWrWr3/8/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec12.7Datapath + Data Stationary ControlExecReg. FileMemAccessDataMemABSRegFilePCNext PCIRInst. MemDDecodeMemCtrlWB CtrlMrs rtoprsrtfunimexmewbrwvmewbrwvwbrwv3/8/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec12.8Let’s Try it Out10 lw r1, r2(35)14 addI r2, r2, 320 sub r3, r4, r524 beq r6, r7, 10030 ori r8, r9, 1734 add r10, r11, r12100 and r13, r14, 15these addresses are octal3/8/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec12.9Start: Fetch 10ExecReg. FileMemAccessDataMemABSRegFileIRInst. MemDDecodeMemCtrlWB CtrlMrs rtim10 lw r1, r2(35)14 addI r2, r2, 320 sub r3, r4, r524 beq r6, r7, 10030 ori r8, r9, 1734 add r10, r11, r12100 and r13, r14, 15IFPCNext PC10=n n n n3/8/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec12.10Fetch 14, Decode 10ExecReg. FileMemAccessDataMemABSRegFileIRInst. MemDDecodeMemCtrlWB CtrlM2 rtim10 lw r1, r2(35)14 addI r2, r2, 320 sub r3, r4, r524 beq r6, r7, 10030 ori r8, r9, 1734 add r10, r11, r12100 and r13, r14, 15lw r1, r2(35)IDIFPCNext PC14=n n n3/8/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec12.11Fetch 20, Decode 14, Exec 10ExecReg. FileMemAccessDataMemr2BSRegFileIRInst. MemDDecodeMemCtrlWB CtrlM2 rt3510 lw r1, r2(35)14 addI r2, r2, 320 sub r3, r4, r524 beq r6, r7, 10030 ori r8, r9, 1734 add r10, r11, r12100 and r13, r14, 15lw r1addI r2, r2, 3IDIFEXPCNext PC20=nn3/8/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec12.12Fetch 24, Decode 20, Exec 14, Mem 10ExecReg. FileMemAccessDataMemr2Br2+35RegFileIRInst. MemDDecodeMemCtrlWB CtrlM45310 lw r1, r2(35)14 addI r2, r2, 320 sub r3, r4, r524 beq r6, r7, 10030 ori r8, r9, 1734 add r10, r11, r12100 and r13, r14, 15lw r1sub r3, r4, r5addI r2, r2, 3IDIFEXM PCNext PC24=n3/8/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec12.13Fetch 30, Dcd 24, Ex 20, Mem 14, WB 10ExecReg. FileMemAccessDataMemr4r5r2+3RegFileIRInst. MemDDecodeMemCtrlWB CtrlM[r2+35]6710 lw r1, r2(35)14 addI r2, r2, 320 sub r3, r4, r524 beq r6, r7, 10030 ori r8, r9, 1734 add r10, r11, r12100 and r13, r14, 15lw r1beq r6, r7 100addI r2sub r3IDIFEXM WB PCNext PC30=Note Delayed Branch: always execute ori after beq3/8/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec12.14Fetch 100, Dcd 30, Ex 24, Mem 20, WB 14ExecReg. FileMemAccessDataMemr6r7r2+3RegFileIRInst. MemDDecodeMemCtrlWB Ctrlr1=M[r2+35]9xx10 lw r1, r2(35)14 addI r2, r2, 320 sub r3, r4, r524 beq r6, r7, 10030 ori r8, r9, 1734 add r10, r11, r12100 and r13, r14, 15beqaddI r2sub r3r4-r5100ori r8, r9 17IDIFEXM WB PCNext PC100=3/8/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec12.15Fetch 104, Dcd 100, Ex 30, Mem 24, WB 20ExecReg. FileMemAccessDataMemRegFileIRInst. MemDDecodeMemCtrlWB Ctrl10 lw r1, r2(35)14 addI r2, r2, 320 sub r3, r4, r524 beq r6, r7, 10030 ori r8, r9, 1734 add r10, r11, r12100 and r13, r14, 15IDEXM WB PCNext PC___=Fill it in yourself!?3/8/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec12.16Fetch 110, Dcd 104, Ex 100, Mem 30, WB 24ExecReg. FileMemAccessDataMemRegFileIRInst. MemDDecodeMemCtrlWB Ctrl10 lw r1, r2(35)14 addI r2, r2, 320 sub r3, r4, r524 beq r6, r7, 10030 ori r8, r9, 1734 add r10, r11, r12100 and r13, r14, 15EXM WB PCNext PC___=Fill it in yourself!?????3/8/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec12.17Fetch 114, Dcd 110, Ex 104, Mem 100, WB 30ExecReg. FileMemAccessDataMemRegFileIRInst. MemDDecodeMemCtrlWB Ctrl10 lw r1, r2(35)14 addI r2, r2, 320 sub r3, r4, r524 beq r6, r7, 10030 ori r8, r9, 1734 add r10, r11, r12100 and r13, r14, 15M WB PCNext PC___=Fill it in yourself!??????3/8/04 ©UCB Spring 2004CS152 / Kubiatowicz Lec12.18Pipelined Processor° Separate
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