Recap Summary of Pipelining Basics 5 stages CS152 Computer Architecture and Engineering Lecture 14 Fetch Fetch instruction from memory Decode get register values and decode control information Execute Execute arithmetic operations calculate addresses Memory Do memory ops load or store Writeback Write results back to registers I e COMMIT Pipelining Control Continued Introduction to Advanced Pipelining Pipelines pass control information down the pipe just as data moves down pipe October 19 2001 Forwarding Stalls handled by local control John Kubiatowicz http cs berkeley edu kubitron lecture slides http www inst eecs berkeley edu cs152 10 19 01 UCB Fall 2001 CS152 Kubiatowicz Lec14 1 Recap Can pipelining get us into trouble Yes Pipeline Hazards UCB Fall 2001 10 19 01 CS152 Kubiatowicz Lec14 2 UCB Fall 2001 Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Clock 1st lw Ifetch Reg Dec 2nd lw Ifetch 3rd lw Exec Mem Wr Reg Dec Exec Mem Wr Ifetch Reg Dec Exec Mem Wr The five independent functional units in the pipeline datapath are Instruction Memory for the Ifetch stage Register File s Read ports bus A and busB for the Reg Dec stage ALU for the Exec stage Data Memory for the Mem stage Register File s Write port bus W for the Wr stage Can always resolve hazards by waiting 10 19 01 Increasing length of pipe increases impact of hazards pipelining helps instruction bandwidth not latency Pipelining the Load Instruction structural hazards attempt to use the same resource two different ways at the same time E g combined washer dryer would be a structural hazard or folder busy doing something else watching TV data hazards attempt to use item before it is ready E g one sock of pair in dryer and one in washer can t fold until get sock from washer through dryer instruction depends on result of prior instruction still in the pipeline control hazards attempt to make a decision before condition is evaulated E g washing football uniforms and need to get proper detergent level need to see after dryer before next load in branch instructions pipeline control must detect the hazard take action or delay action to resolve hazards Balancing length of instructions makes pipelining much smoother CS152 Kubiatowicz Lec14 3 10 19 01 UCB Fall 2001 CS152 Kubiatowicz Lec14 4 The Four Stages of R type Cycle 1 Cycle 2 Pipelining the R type and Load Instruction Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Clock R type Ifetch Reg Dec Exec R type Ifetch Wr R type Ifetch Instruction Fetch Reg Dec Exec Ifetch Reg Dec Exec Ifetch Reg Dec Load Fetch the instruction from the Instruction Memory R type Ifetch Reg Dec Registers Fetch and Instruction Decode Ops We have a problem Wr Wr Exec Mem Wr Reg Dec Exec Wr R type Ifetch Reg Dec Exec Wr Exec ALU operates on the two register operands Update PC We have pipeline conflict or structural hazard Two instructions try to write to the register file at the same time Only one write port Wr Write the ALU output back to the register file 10 19 01 CS152 Kubiatowicz Lec14 5 UCB Fall 2001 10 19 01 Important Observation Solution 1 Insert Bubble into the Pipeline Each functional unit can only be used once per instruction Cycle 1 Cycle 2 Ifetch Load Load uses Register File s Write Port during its 5th stage Load 2 3 Ifetch Reg Dec Exec 4 5 Mem Wr Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Clock Each functional unit must be used at the same stage for all instructions 1 CS152 Kubiatowicz Lec14 6 UCB Fall 2001 Reg Dec Exec Ifetch Reg Dec R type Ifetch Wr Exec Reg Dec R type Ifetch Mem Wr Exec Wr Reg Dec Pipeline R type Ifetch Ifetch R type uses Register File s Write Port during its 4th stage 1 R type Ifetch 2 3 Reg Dec Exec 4 Exec Bubble Reg Dec Wr Exec Reg Dec Wr Exec Insert a bubble into the pipeline to prevent 2 writes at the same cycle Wr The control logic can be complex Lose instruction fetch and issue opportunity 2 ways to solve this pipeline hazard No instruction is started in Cycle 6 10 19 01 UCB Fall 2001 CS152 Kubiatowicz Lec14 7 10 19 01 UCB Fall 2001 CS152 Kubiatowicz Lec14 8 Solution 2 Delay R type s Write by One Cycle Modified Control Datapath Delay R type s register write by one cycle IR Mem PC PC PC 4 Now R type instructions also use Reg File s write port at Stage 5 Mem stage is a NOOP stage nothing is being done Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 S A or ZX M S M S Clock Reg Dec Exec Mem Wr Ifetch Reg Dec Exec Mem Wr Ifetch Reg Dec Exec Mem Wr Reg Dec Exec Mem Wr Reg Dec Exec Mem Load R type Ifetch R type Ifetch 10 19 01 Wr CS152 Kubiatowicz Lec14 9 UCB Fall 2001 The Four Stages of Store Cycle 1 Cycle 2 Store Ifetch Reg Dec M Mem S Mem S B R rd M A if Cond PC PC SX D UCB Fall 2001 M S B 10 19 01 Cycle 3 Cycle 4 Exec S A SX CS152 Kubiatowicz Lec14 10 The Three Stages of Beq Mem Cycle 1 Cycle 2 Wr Beq Ifetch Instruction Fetch Reg Dec Exec Mem Wr Fetch the instruction from the Instruction Memory Reg Dec Registers Fetch and Instruction Decode Reg Dec Registers Fetch and Instruction Decode Exec Calculate the memory address Exec Mem Write the data into the Data Memory UCB Fall 2001 Ifetch Cycle 3 Cycle 4 Ifetch Instruction Fetch Fetch the instruction from the Instruction Memory 10 19 01 R rt M PC R type R rd M Next PC R type Ifetch S A SX Reg File S A B Data Mem Wr Mem Access Mem A R rs B R rt Equal 5 Exec Reg Dec 4 Reg File R type Ifetch 3 Exec IR 2 Inst Mem 1 compares the two register operand select correct branch target address latch into PC CS152 Kubiatowicz Lec14 11 10 19 01 UCB Fall 2001 CS152 Kubiatowicz Lec14 12 Control Diagram Administrivia Updated Lab 5 schedule IR Mem PC PC PC 4 Up there now sorry about that Mail problem 0 to TA by Monday night at Midnight A R rs B R rt Evaluation of your partners Mail Lab 5 breakdowns to your TAs by Wednesday at Midnight Mem S B We are not going to extend the deadline You have 3 weekends to work on it Wednesday advanced pipelining A M S Out of order execution register renaming Reorder buffers Solutions to Midterm I are up B D 10 19 01 Get started on Lab 5 Pipelining is difficult to get right Be sure that we will test gotcha cases in our mystery programs …
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