CS 152 Computer Architecture and Engineering Lecture 12 Memory and Interfaces 2005 10 11 John Lazzaro www cs berkeley edu lazzaro TAs David Marquardt and Udam Saini www inst eecs berkeley edu cs152 CS 152 L12 Memory and Interfaces UC Regents Fall 2005 UCB Last Time 1 T DRAM cells Vdd Bit Line Word Line Word Line Vdd Capacitor Bit Line Bit Line n oxide n oxide pWord Line and Vdd run on z axis CS 152 L12 Memory and Interfaces Why Vcap values start out at ground Vdd Vcap Diode leakage current UC Regents Fall 2005 UCB Today Memory Technology Wrap Up Static Memory Circuits For SRAM memory cells and for flip flops Memory Arrays Row decoders column sense amps array sizing DRAM Interfaces How the SDRAM chips on the Calinx board work CS 152 L12 Memory and Interfaces UC Regents Fall 2005 UCB Inverters CS 152 L12 Memory and Interfaces UC Regents Fall 2005 UCB Inverters Circuits and Layout Vdd symbol Vin CS 152 L12 Memory and Interfaces Vout Vin Vout UC Regents Fall 2005 UCB Inverter Die Cross Section Vout Vin n Vin oxide n p oxide p n n well p Vin CS 152 L12 Memory and Interfaces Vout UC Regents Fall 2005 UCB Inverters n fet Transistor Equation If Vgs Vt and Vds Vgs Vt Ids k 2 W L Vgs Vt 2 Vin Vd Ids Vg Vs Vout Otherwise if Vgs Vt Ids k W L Vgs Vt Vds Otherwise Ids 0 but really Io exp Vg Vs Vo 1 exp Vds Vo Note Vt is transistor threshold was formerly Vth Also Vt is actually Vt Vs sqrt Vs CS 152 L12 Memory and Interfaces UC Regents Fall 2005 UCB Inverters p fet Transistor Equation Vin Vg Vs Isd Vd If Vsg Vt and Vsd Vsg Vt Isd k 2 W L Vsg Vt 2 Vout Otherwise if Vsg Vt Isd k W L Vsg Vt Vsd Otherwise Isd 0 but again in reality there is a leakage current Note Vt for p Fet and n Fet are different Also true for k fab constant kp kn due to electrons being faster than holes CS 152 L12 Memory and Interfaces UC Regents Fall 2005 UCB Inverters with Vin Gnd Vout Vdd Is Vsd Vsg Vt once Vout is Vdd Is Vsg Vt Vin Vs Isd Vd Vd Isd k W L Vsg Vt Vsd Vout Ids This goes as close to 0 as it can while still supplying the leakage current Vs Ids 0 but really a small leakage current CS 152 L12 Memory and Interfaces UC Regents Fall 2005 UCB Inverters with Vin Vdd Vout Gnd Isd 0 but really a small leakage current Vs Isd Vd Vin Vd Vout This goes as close to 0 as it can while still supplying the leakage current Ids Vs Is Vds Vgs Vt once Vout is Gnd Is Vgs Vt Ids k W L Vgs Vt Vds CS 152 L12 Memory and Interfaces UC Regents Fall 2005 UCB Calculating the inverter threshold Vth Tie output to input Vth Vth Vin Vs Isd Vd Vd Ids Assume voltage is somewhere near the middle Vout For nfet is Vds Vgs Vt For pfet is Vsd Vsg Vt No by definition Use Vs Ids kn W L Vth Vtn Vth Isd kp W L Vdd Vth Vtp Vdd Vth To compute the exact voltage in the middle CS 152 L12 Memory and Interfaces UC Regents Fall 2005 UCB Question What happens when Vin Vs Isd Vd Vd Ids Vs Vout Vin Vs Isd Vd Vd Vout Ids Vs Stays at Vth until a tiny amount of Vin noise appears Then output goes to Vdd or Gnd until Vin noise flips it back the other way Lesson at Vth small dVin make big dVout CS 152 L12 Memory and Interfaces UC Regents Fall 2005 UCB Static Memory Circuits Dynamic Memory Circuit remembers for a fraction of a second Static Memory Circuit remembers as long as the power is on Non volatile Memory Circuit remembers for many years even if power is off CS 152 L12 Memory and Interfaces UC Regents Fall 2005 UCB Recall DRAM cell 1 T 1 C Word Line Row Column Bit Line Column Row Word Line Vdd Bit Line CS 152 L12 Memory and Interfaces UC Regents Fall 2005 UCB Idea Store each bit with its complement x x Row Why Gnd Vdd Vdd Gnd We can use the redundant representation to compensate for noise and leakage CS 152 L12 Memory and Interfaces UC Regents Fall 2005 UCB Case 1 x Gnd x Vdd x x Row Isd Gnd Vdd Ids CS 152 L12 Memory and Interfaces UC Regents Fall 2005 UCB Case 2 x Vdd x Gnd x x Row Isd Gnd Vdd Ids CS 152 L12 Memory and Interfaces UC Regents Fall 2005 UCB Combine both cases to complete circuit noise noise Gnd Vdd Vth Vth Vdd Gnd Crosscoupled inverters x CS 152 L12 Memory and Interfaces x UC Regents Fall 2005 UCB SRAM Challenge 1 It s so big SRAM area is 6X 10X DRAM area same generation Cell has both transistor types Capacitors are usually parasitic capacitance of wires and transistors CS 152 L12 Memory and Interfaces Vdd AND Gnd More contacts more devices t wo bit lines UC Regents Fall 2005 UCB Challenge 2 Writing is a fight When word line goes high bitlines fight with cell inverters to flip the bit must win quickly Solution tune W L of cell driver transistors Initial state Vdd Bitline drives Gnd CS 152 L12 Memory and Interfaces Initial state Gnd Bitline drives Vdd UC Regents Fall 2005 UCB Challenge 3 Preserving state on read When word line goes high on read cell inverters must drive large bitline capacitance quickly to preser ve state on its small cell capacitances Cell state Vdd Bitline a big capacitor CS 152 L12 Memory and Interfaces Cell state Gnd Bitline a big capacitor UC Regents Fall 2005 UCB SRAM vs DRAM pros and cons Big win for DRAM DRAM has a 6 10X density advantage at the same technology generation SRAM advantages SRAM has deterministic latency its cells do not need to be refreshed SRAM is much faster transistors drive bitlines on reads SRAM easy to design in logic fabrication process and premium logic processes have SRAM add ons CS 152 L12 Memory and Interfaces UC Regents Fall 2005 UCB Flip Flops Revisited CS 152 L12 Memory and Interfaces UC Regents Fall 2005 UCB Recall Static RAM cell 6 Transistors noise noise Gnd Vdd Vth Vth Vdd Gnd Crosscoupled inverters x CS 152 L12 Memory and Interfaces x UC Regents Fall 2005 UCB 8 8 Recall Positive edge triggered flip flop 8 8 A flip flop samples right before D Q 12 1 3 8 8 1 5 the edge and then holds value 8 8 1 5 4 2 1 4 3 0 12 1 3 4 2 1 4 3 5 5 164 276 164 276 Sampling 1869 Holds 1869 circuit value 8 8 8 1 5 8 8 8 8 8 1 5 4 2 1 4 3 012 34 5 16 Transistors Makes …
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