CS 152 L07 Single Cycle 2 (1) UC Regents Fall 2004 © UCB2004-09-21John Lazzaro(www.cs.berkeley.edu/~lazzaro)Dave Patterson (www.cs.berkeley.edu/~patterson)www-inst.eecs.berkeley.edu/~cs152/CS152 – Computer Architecture andEngineeringLecture 7 – (Design Notebook+)Single Cycle ControlCS 152 L07 Single Cycle 2 (2) UC Regents Fall 2004 © UCBReview°5 steps to design a processor1. Analyze instruction set => datapath requirements2. Select set of datapath components & establish clock methodology3. Assemble datapath meeting the requirements4. Analyze implementation of each instruction to determine setting of control points that effects the register transfer.5. Assemble the control logic (This Lecture)°MIPS makes it easier• Instructions same size; Source registers, immediates always in same place• Operations always on registers/immediates°Single cycle datapath => CPI=1, CCT => longCS 152 L07 Single Cycle 2 (3) UC Regents Fall 2004 © UCBWhy should you keep a design notebook?°Keep track of the design decisions and the reasons behind them• Otherwise, it will be hard to debug and/or refine the design• Write it down so that can remember in long project: 2 weeks ->2 yrs• Others can review notebook to see what happened°Record insights you have on certain aspect of the design as they come up°Record of the different design & debug experiments• Memory can fail when very tired°Industry practice: learn from others mistakesCS 152 L07 Single Cycle 2 (4) UC Regents Fall 2004 © UCBWhy do we keep it on-line?°You need to force yourself to take notes!• Open a window and leave an editor running while you work1) Acts as reminder to take notes2) Makes it easy to take notes• 1) + 2) => will actually do it°Take advantage of the window system’s “cut and paste” features°It is much easier to read your typing than your writing°Also, paper log books have problems• Limited capacity => end up with many books• May not have right book with you at time vs. networked screens• Can use computer to search files/index files to find what looking forCS 152 L07 Single Cycle 2 (5) UC Regents Fall 2004 © UCBHow should you do it?°Keep it simple• DON’T make it so elaborate that you won’t use (fonts, layout, ...)°Separate the entries by dates• type “date” command in another window and cut&paste°Start day with problems going to work on today°Record output of simulation into log with cut&paste; add date• May help sort out which version of simulation did what°Record key email with cut&paste°Record of what works & doesn’t helps team decide what went wrong after you left°Index: write a one-line summary of what you did at end of each dayCS 152 L07 Single Cycle 2 (6) UC Regents Fall 2004 © UCBOn-line Notebook Example°Refer to the handout “Example of On-Line Log Book” on CS 152 home page:http://www-inst.eecs.berkeley.edu/~cs152/ handouts/online_notebook_example.htmlCS 152 L07 Single Cycle 2 (7) UC Regents Fall 2004 © UCBRecap: Putting it All Together: 1 Cycle Datapathimm1632ALUctrbusWRegWr3232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDstExtenderMux3216imm16ALUSrcExtOpMuxMemtoRegClkData InWrEn32AdrDataMemoryMemWrALUZeroInstruction<31:0>010101<21:25><16:20><11:15><0:15>Imm16RdRtRsAdderAdderPCClk00Mux4PCSrcPC ExtAdrInstMemoryClkCS 152 L07 Single Cycle 2 (8) UC Regents Fall 2004 © UCBRecap: The MIPS-lite Subset°ADD and subtract• add rd, rs, rt• sub rd, rs, rt°OR Imm:• ori rt, rs, imm16°LOAD and STORE• lw rt, rs, imm16• sw rt, rs, imm16°BRANCH:• beq rs, rt, imm16op rs rt rd shamt funct0611162126316 bits 6 bits5 bits5 bits5 bits5 bitsop rs rt immediate0162126316 bits 16 bits5 bits5 bitsCS 152 L07 Single Cycle 2 (9) UC Regents Fall 2004 © UCBMeaning of the Control Signals° ExtOp: “zero”, “sign”° ALUsrc: 0 regB; 1 immed° ALUctr: “add”, “sub”, “or”° MemWr: 1 write memory° MemtoReg: 0 ALU; 1 Mem° RegDst: 0 “rt”; 1 “rd”° RegWr: 1 write register32ALUctrClkbusWRegWr3232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDstExtenderMux3216imm16ALUSrcExtOpMuxMemtoRegClkData InWrEn32AdrDataMemoryMemWrALUZero010101CS 152 L07 Single Cycle 2 (10) UC Regents Fall 2004 © UCBTwo equivalent ways to specify control°Book does left version (Fig 5.18, p. 308)• Book combines all ALU instructions as “R-format” vs. separate instructions (add …)• Good news: lecture different view than book°We’ll do right by committee, 1 at a timeControlline 0Controlline 1…Controlline nAddU A BSubUORILWSWBEQ X YAddU SubU ORI LW SW BEQControlline 0A XControlline 1…Controlline nB Y(Rotate about 45degree axis)CS 152 L07 Single Cycle 2 (11) UC Regents Fall 2004 © UCBSetting PC Source Control Signal°PCSrc: 0 PC <= PC + 4 1 PC <= PC + 4 + {SignExt(Im16), 2’b00}°Later in lecture: higher-level connection between mux and branch condAdrInstMemoryAdderAdderPCClk00Mux4PCSrcPC Extimm16Answer? AddU SubU ORI LW SW BEQ0 0 0 0 0 0 01 0 0 0 0 0 12 0 0 0 0 1 13 0 0 0 1 1 14 0 0 1 1 1 15 0 1 1 1 1 16 1 1 1 1 1 17 1 1 1 1 1 X8 X X X X X 19 None of the aboveCS 152 L07 Single Cycle 2 (12) UC Regents Fall 2004 © UCBSetting PC Source Control Signal°PCSrc: 0 PC <= PC + 4 1 PC <= PC + 4 + {SignExt(Im16), 2’b00}°Later in lecture: higher-level connection between mux and branch condAdrInstMemoryAdderAdderPCClk00Mux4PCSrcPC Extimm16Answer? AddU SubU ORI LW SW BEQ0 0 0 0 0 0 01 0 0 0 0 0 12 0 0 0 0 1 13 0 0 0 1 1 14 0 0 1 1 1 15 0 1 1 1 1 16 1 1 1 1 1 17 1 1 1 1 1 X8 X X X X X 19 None of the aboveCS 152 L07 Single Cycle 2 (13) UC Regents Fall 2004 © UCBMeaning of the Control Signals°ExtOp: 0 “zero” ; 1 “sign”°ALUsrc: 0 regB; 1 immed°ALUctr: “add”, “sub”, “or”° MemWr: 1 write memory° MemtoReg: 0 ALU; 1 Mem° RegDst: 0 “rt”; 1 “rd”° RegWr: 1 write register32ALUctrClkbusWRegWr3232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdRegDstExtenderMux3216imm16ALUSrcExtOpMuxMemtoRegClkData InWrEn32AdrDataMemoryMemWrALUZero010101CS 152 L07 Single Cycle 2 (14) UC Regents Fall 2004 © UCBSpecify ALU source mux Control°ALUsrc: 0 reg as ALU B input; 1 immediate as ALU B inputClkbusW3232busA32busB55 5Rw Ra Rb32 32-bitRegistersRsRtRtRdExtenderMux3216imm16ALUSrcExtOpData In32ALU0101Answer? AddU SubU ORI LW SW BEQ0 0 0 0 0 0 01 0 0 0 0 0 12 0 0 0 0 1 13 0 0 1 1 1 04 0 0 0 1 1 15 0 0 0 1 1 X6 1 1 1 1 1 17 1 1 1 1 1 X8 X X X X X 19 None of the aboveCS 152 L07 Single
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