Recap Processor Design is a Process Bottom up CS 152 Computer Architecture and Engineering Lecture 9 assemble components in target technology to establish critical timing Top down specify component behavior from high level requirements Designing a Multicycle Processor Iterative refinement establish partial solution expand and improve Instruction Set Architecture February 26 2003 processor datapath control John Kubiatowicz www cs berkeley edu kubitron Reg File Mux ALU Reg Mem Decoder Sequencer lecture slides http inst eecs berkeley edu cs152 Cells 2 26 03 CS152 Kubiatowicz Lec9 1 UCB Spring 2003 Recap A Single Cycle Datapath 2 26 03 Gates Recap The Truth Table for the Main Control RegDst Instruction 31 0 1 Mux 0 RegWr 5 Rs 5 Rt Rs ALUctr 5 busA 0 1 32 Data In 32 Clk RegDst ALUSrc MemtoReg RegWrite MemWrite Branch Jump ExtOp ALUop Symbolic ALUop 2 ALUop 1 ALUop 0 MemtoReg 0 32 1 Data Memory ALUSrc ExtOp 2 26 03 UCB Spring 2003 6 ALUop ALU Control Local ALUctr 3 3 Imm16 32 WrEn Adr Main Control op Mux 16 Extender imm16 32 Mux 32 Clk Rw Ra Rb 32 32 bit Registers busB 32 Rd Equal MemWr ALU busW Rt 6 0 15 Clk 11 15 Instruction Fetch Unit 16 20 RegDst Rt 21 25 Rd func ALUSrc op nPC sel CS152 Kubiatowicz Lec9 2 UCB Spring 2003 CS152 Kubiatowicz Lec9 3 2 26 03 00 0000 R type 1 0 0 1 0 0 0 x R type 1 0 0 00 1101 10 0011 10 1011 00 0100 00 0010 ori lw sw beq jump 0 0 x x x 1 1 1 0 x 0 1 x x x 1 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 1 1 x x Or Add Add Subtract xxx 0 0 0 x 0 1 0 0 x 0 0 0 0 x 1 UCB Spring 2003 CS152 Kubiatowicz Lec9 4 Recap PLA Implementation of the Main Control op 5 op 5 0 op 5 0 op 5 0 op 5 0 Recap Systematic Generation of Control op 5 0 op 0 OPcode Decode lw sw beq jump RegWrite ALUSrc microinstruction Conditions ori Instruction R type Control Points RegDst MemtoReg MemWrite Branch Jump ExtOp ALUop 2 ALUop 1 ALUop 0 2 26 03 UCB Spring 2003 CS152 Kubiatowicz Lec9 5 The Big Picture Where are We Now Control Logic Store PLA ROM Datapath In our single cycle processor each instruction is realized by exactly one control command or microinstruction in general the controller is a finite state machine microinstruction can also control sequencing see later 2 26 03 CS152 Kubiatowicz Lec9 6 UCB Spring 2003 Abstract View of our single cycle processor Main Control op The Five Classic Components of a Computer ALU control fun Processor MemWr MemRd MemWr RegDst RegWr Result Store Reg Wrt Data Mem ALU Mem Access Ext Register Fetch Instruction Fetch Today s Topic Designing the Datapath for the Multiple Clock Cycle Datapath PC Output Next PC Datapath Equal nPC sel Memory ExtOp ALUSrc ALUctr Input Control looks like a FSM with PC as state 2 26 03 UCB Spring 2003 CS152 Kubiatowicz Lec9 7 2 26 03 UCB Spring 2003 CS152 Kubiatowicz Lec9 8 What s wrong with our CPI 1 processor Arithmetic Logical PC Inst Memory Memory Access Time Physics fast memories are small large memories are slow Reg File mux ALU mux Storage Array setup selected word line Load PC Inst Memory mux Reg File Critical Path ALU Data Mem Store PC Inst Memory Reg File ALU Data Mem storage cell Branch PC Inst Memory Reg File mux cmp address mux setup bit line address decoder sense amps question register file vs memory mux All instructions take as much time as the slowest Processor Real memory is not as nice as our idealized memory Cache 2 3 time periods CS152 Kubiatowicz Lec9 9 UCB Spring 2003 2 26 03 Cut combinational dependency graph and insert register latch Do same work in two fast cycles rather than one slow one May be able to short circuit path and remove some components for some instructions storage element Acyclic Combinational Logic A storage element Acyclic Combinational Logic B PC Old Value Clk to Q New Value Instruction Memoey Access Time New Value Rs Rt Rd Op Func Old Value ALUctr Old Value ExtOp Old Value New Value ALUSrc Old Value New Value MemtoReg Old Value New Value RegWr Old Value New Value busB Delay through Control Logic New Value storage element Register Write Occurs Register File Access Time New Value Old Value Delay through Extender Mux Old Value New Value ALU Delay Address storage element UCB Spring 2003 CS152 Kubiatowicz Lec9 10 Clk busA 2 26 03 20 50 time periods UCB Spring 2003 storage element memory Worst Case Timing Load Reducing Cycle Time Acyclic Combinational Logic L2 Cache 1 time period cannot always get the job done in one short cycle 2 26 03 mem bus Long Cycle Time proc bus Use a hierarchy of memories Old Value New Value Data Memory Access Time CS152 Kubiatowicz Lec9 11 busW 2 26 03 Old Value UCB Spring 2003 New CS152 Kubiatowicz Lec9 12 Basic Limits on Cycle Time Partitioning the CPI 1 Datapath Next address logic Add registers between smallest steps PC branch PC offset PC 4 Instruction Fetch CS152 Kubiatowicz Lec9 13 UCB Spring 2003 MemWr Result Store RegDst RegWr Reg File Data Mem MemRd MemWr Mem Access ALUctr ALUSrc Place enables on all registers 2 26 03 UCB Spring 2003 CS152 Kubiatowicz Lec9 14 Reg File RegDst RegWr MemToReg MemRd MemWr ALUctr Read Chapter 5 This lecture and next one slightly different from the book M Result Store Operand Fetch Instruction Fetch B S Data Mem A Mem Access IR PC Reg File Exec Administrative Issues Ext ALUSrc ALU Equal nPC sel E ExtOp Example Multicycle Datapath PC Next PC Result Store MemWr RegDst RegWr Reg File Exec Data Mem MemRd MemWr ALUctr Mem Access Operand Fetch Instruction Fetch ExtOp nPC sel PC Next PC 2 26 03 ALUSrc Control R A B Operand Fetch ALU operation Instruction Fetch nPC sel A R rs Next PC Equal Register Access ExtOp InstructionReg Mem PC Midterm two weeks from today Wednesday 3 12 5 30pm to 8 30pm location TBA No class on that day Pencil calculator one 8 5 x 11 both sides of handwritten notes Sit in every other chair every other row Meet at LaVal s pizza after the midterm Critical Path 2 26 03 UCB Spring 2003 CS152 Kubiatowicz Lec9 15 2 26 03 UCB Spring 2003 CS152 Kubiatowicz Lec9 16 Step 4 R rtype add sub Recall Step by step Processor Design Logical Register Transfer Step 1 ISA Logical Register Transfers inst Logical Register Transfers ADDU R rd R rs R rt PC PC 4 Physical Register Transfers inst Step 3 RTL Components Datapath Physical Register Transfers IR MEM pc Time Step 2 Components of the Datapath ADDU A R rs B R rt S A B R rd S Step 4 Datapath Logical RTs Physical RTs PC PC 4 Step …
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