Slide 1Slide 2Slide 3Slide 4Slide 5Slide 6Slide 7Slide 8Slide 9Slide 10Slide 11Slide 12Slide 13Slide 14Slide 15Slide 16Slide 17Slide 18Slide 19Slide 20Slide 21Slide 22Slide 23Slide 24Slide 25Slide 26Slide 27Slide 28Slide 29Slide 30Slide 31Slide 32Slide 33Slide 34Slide 35Slide 36Slide 37Slide 38Slide 39Slide 40UC Regents Fall 2005 © UCBCS 152 L12: Memory and Interfaces2005-10-11John Lazzaro (www.cs.berkeley.edu/~lazzaro)CS 152 Computer Architecture and EngineeringLecture 12 – Memory and Interfaceswww-inst.eecs.berkeley.edu/~cs152/TAs: David Marquardt and Udam SainiUC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesLast Time: 1-T DRAM cellsVddCapacitor “Word Line”“Bit Line”p-oxiden+n+oxide------“Bit Line”Word Line and Vdd run on “z-axis”Word LineVdd“Bit Line”VddDiode leakagecurrent.Why Vcap values start out at ground.VcapUC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesToday: Memory Technology Wrap-UpStatic Memory Circuits: For SRAM memory cells and for flip-flops.Memory Arrays: Row decoders, column sense amps, array sizing.DRAM Interfaces: How the SDRAM chips on the Calinx board work.UC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesInvertersUC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesInverters: Circuits and LayoutVoutVinVdd symbolVin VoutUC Regents Fall 2005 © UCBCS 152 L12: Memory and Interfacesp-oxiden+n+n-welloxidep+p+n+VoutVin VinInverter: Die Cross SectionVoutVinUC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesInverters: n-fet Transistor EquationI dsVoutVinVsVdV gIf Vgs > Vt and Vds > Vgs - Vt :Ids = (k/2) (W/L) [Vgs -Vt]^2 Ids ≈0, but really = Io [exp((κVg - Vs)/Vo)] [1 - exp(-Vds/Vo)]Otherwise:Otherwise, if Vgs > Vt :Ids = k (W/L) [Vgs -Vt] [Vds]Note: Vt is transistor threshold, was formerly Vth. Also, Vt is actually Vt(Vs) ∼sqrt(Vs).UC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesInverters: p-fet Transistor EquationVoutVinVsVdV gIf Vsg > Vt and Vsd > Vsg - Vt :Isd = (k/2) (W/L) [Vsg -Vt]^2 Isd ≈0, but again, in reality there is a “leakage” current.Otherwise:Otherwise, if Vsg > Vt :Isd = k (W/L) [Vsg -Vt] [Vsd]Note: Vt for p-Fet and n-Fet are different. Also true for “k” (fab constant). kp < kn, due to electrons being faster than holes. I sdUC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesInverters with Vin = Gnd, Vout = VddI dsVoutVinVsVdVsVdI sdIs Vsg > Vt ?Isd = k (W/L) [Vsg -Vt] [Vsd]Ids ≈0, but really a small leakage currentIs Vsd > Vsg - Vt once Vout is Vdd?This goes as close to 0 as it can while still supplying the leakage current.UC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesInverters with Vin = Vdd, Vout = GndI dsVoutVinVsVdVsVdI sdIs Vgs > Vt ?Ids = k (W/L) [Vgs -Vt] [Vds]Is Vds > Vgs - Vt once Vout is Gnd?Isd ≈0, but really a small leakage currentThis goes as close to 0 as it can while still supplying the leakage current.UC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesCalculating the inverter threshold (Vth)Assume voltage is “somewhere near the middle”For nfet, is Vds > Vgs - Vt ?For pfet, is Vsd > Vsg - Vt ?No, by definition! Use:Isd = kp (W/L) [Vdd-Vth -Vtp] [Vdd - Vth]Ids = kn (W/L) [Vth -Vtn] [Vth]To compute the exact “voltage in the middle”.I dsVoutVinVsVdVsVdI sdTie output to input.VthVthUC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesQuestion: What happens when ...I dsVoutVinVsVdVsVdI sdI dsVoutVinVsVdVsVdI sdStays at Vth until a tiny amount of Vin noise appears.Then output goes to Vdd or Gnd until ...... Vin noise flips it back the other way. Lesson: at Vth, small dVin make big dVoutUC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesStatic Memory CircuitsDynamic Memory: Circuit remembers for a fraction of a second.Non-volatile Memory: Circuit remembers for many years, even if power is off.Static Memory: Circuit remembers as long as the power is on.UC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesRecall DRAM cell: 1 T + 1 C“Word Line”Bit Line“Column” “Row” Word LineVdd“Bit Line”“Row” “Column”UC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesIdea: Store each bit with its complementx “Row” x! Gnd Vdd Vdd Gnd We can use the redundant representation to compensate for noise and leakage.Why?UC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesCase #1: x = Gnd, x! = Vdd ...x “Row” x! Gnd Vdd I dsI sdUC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesCase #2: x = Vdd, x! = Gnd ...x “Row” x! Gnd Vdd I sdI dsUC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesCombine both cases to complete circuitx! x Gnd Vdd Vdd Gnd Vth Vth noise noise “Cross- coupled inverters”UC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesSRAM Challenge #1: It’s so big!Capacitors are usually “parasitic”capacitance of wires and transistors.Cell has both transistor typesVdd AND GndMore contacts, more devices, two bit lines ...SRAM area is 6X-10X DRAM area, same generation ...UC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesChallenge #2: Writing is a “fight” When word line goes high, bitlines “fight” with cell inverters to “flip the bit” -- must win quickly! Solution: tune W/L of cell & driver transistorsInitialstateVddInitialstateGndBitline drives GndBitline drives VddUC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesChallenge #3: Preserving state on readWhen word line goes high on read, cell inverters must drive large bitline capacitance quickly, to preserve state on its small cell capacitances CellstateVddCellstateGndBitline a big capacitorBitline a big capacitorUC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesSRAM vs DRAM, pros and consDRAM has a 6-10X density advantage at the same technology generation.Big win for DRAMSRAM is much faster: transistors drive bitlines on reads.SRAM easy to design in logic fabrication process (and premium logic processes have SRAM add-ons)SRAM has deterministic latency: its cells do not need to be refreshed.SRAM advantagesUC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesFlip Flops RevisitedUC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesRecall: Static RAM cell (6 Transistors)x! x Gnd Vdd Vdd Gnd Vth Vth noise noise “Cross- coupled inverters”UC Regents Fall 2005 © UCBCS 152 L12: Memory and InterfacesRecall: Positive edge-triggered flip-flopD
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